diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-15 23:51:54 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-09 18:13:45 +0000 |
| commit | 822b267a8cfd8127f4b2a35942c01589a604ee5f (patch) | |
| tree | 8750ad8f2deba6bfb0e3b53516ddd8f30add44e8 /src/mainboard/asrock/b85m_pro4 | |
| parent | 03f0e43a3c4172941f2eadf30f89413632b90cb4 (diff) | |
mb/asrock/b85m_pro4: Properly select muxed functions
The old values were completely out of whack. Use the same settings as
vendor firmware. The SUPERIO_NUVOTON_NCT6776_COM_A option overwrites
configured settings, so drop it from Kconfig to prevent conflicts.
Change-Id: I9743741518adc153d594ccae65298c7dcc8a88d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/asrock/b85m_pro4')
| -rw-r--r-- | src/mainboard/asrock/b85m_pro4/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/asrock/b85m_pro4/bootblock.c | 10 |
2 files changed, 7 insertions, 4 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig index 7098f9428e..20ff9b1fcb 100644 --- a/src/mainboard/asrock/b85m_pro4/Kconfig +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A config MAINBOARD_DIR string diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c index f95fb52972..9b3746c521 100644 --- a/src/mainboard/asrock/b85m_pro4/bootblock.c +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -13,9 +13,13 @@ void mainboard_config_superio(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); - /* Select HWM/LED functions instead of floppy functions */ - pnp_write_config(GLOBAL_DEV, 0x1c, 0x03); - pnp_write_config(GLOBAL_DEV, 0x24, 0x24); + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1b, 0x68); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x24, 0x1c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); /* Power RAM in S3 and let the PCH handle power failure actions */ pnp_set_logical_device(ACPI_DEV); |