diff options
author | Angel Pons <th3fanbus@gmail.com> | 2019-11-12 10:05:33 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-19 12:01:45 +0000 |
commit | df248f0c10f77b4de287be7754afadce1abca84c (patch) | |
tree | 36774a619c892d4f7521642210424a4c4b95ef7f /src/mainboard/asrock/b85m_pro4/bootblock.c | |
parent | 5baadba532aec78d76d2ba1efea825b5f9b75efc (diff) |
mb/asrock/b85m_pro4: Add new mainboard
This is a µATX mainboard with a LGA1150 socket and four DDR3 DIMM slots.
Working:
- All four DIMM slots
- Serial port to emit spam
- Some USB ports
- Integrated graphics (libgfxinit)
- HDMI and DVI
- Intel GbE
- All PCIe ports
- Both PCI ports behind the ASM1083 PCI bridge
- At least one SATA port
- RAM initialization with MRC binary
- Flashing with flashrom
- S3 suspend/resume
- Rear audio output
- VBT
- SeaBIOS to boot Arch Linux
Not working:
- PS/2 keyboard (detected as mouse)
Untested:
- The other audio jacks
- S/PDIF
- VGA
- EHCI debug
- Front USB headers
- Non-Linux OSes
- TPM header
- Parallel port
Change-Id: I10a16dfc56f2aa88648c8aaaba4feab40c491504
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36770
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock/b85m_pro4/bootblock.c')
-rw-r--r-- | src/mainboard/asrock/b85m_pro4/bootblock.c | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c new file mode 100644 index 0000000000..6a66121aa6 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select HWM/LED functions instead of floppy functions */ + pnp_write_config(GLOBAL_DEV, 0x1c, 0x03); + pnp_write_config(GLOBAL_DEV, 0x24, 0x24); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} |