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authorArthur Heymans <arthur@aheymans.xyz>2019-11-12 19:11:50 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-18 11:48:35 +0000
commitfa5d0f835b1f3bb8907e616913cbf7b91d09ef26 (patch)
treeaf8d33b500b91fa9e2f1a76d9115086644ccf3d2 /src/mainboard/asrock/b75pro3-m/romstage.c
parent59eb2fdb6b06618311ef118996ca8c1d28a85ffc (diff)
nb/intel/sandybridge: Set up console in bootblock
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/asrock/b75pro3-m/romstage.c')
-rw-r--r--src/mainboard/asrock/b75pro3-m/romstage.c64
1 files changed, 0 insertions, 64 deletions
diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c
deleted file mode 100644
index 983de07ff7..0000000000
--- a/src/mainboard/asrock/b75pro3-m/romstage.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/pci_ops.h>
-#include <device/pnp_ops.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-#include <superio/nuvoton/nct6776/nct6776.h>
-#include <superio/nuvoton/common/nuvoton.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
-
-const struct southbridge_usb_port mainboard_usb_ports[] = {
- { 1, 0, 0 },
- { 1, 0, 0 },
- { 1, 1, 1 },
- { 1, 1, 1 },
- { 1, 1, 2 },
- { 1, 1, 2 },
- { 1, 0, 3 },
- { 1, 0, 3 },
- { 1, 0, 4 },
- { 1, 0, 4 },
- { 1, 0, 6 },
- { 1, 1, 5 },
- { 1, 1, 5 },
- { 1, 0, 6 },
-};
-
-void mainboard_config_superio(void)
-{
- /* Set GPIOs on superio, enable UART */
- nuvoton_pnp_enter_conf_state(SERIAL_DEV);
- pnp_set_logical_device(SERIAL_DEV);
-
- pnp_write_config(SERIAL_DEV, 0x1c, 0x80);
- pnp_write_config(SERIAL_DEV, 0x27, 0x80);
- pnp_write_config(SERIAL_DEV, 0x2a, 0x60);
-
- nuvoton_pnp_exit_conf_state(SERIAL_DEV);
-
- nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
- read_spd(&spd[0], 0x50, id_only);
- read_spd(&spd[1], 0x51, id_only);
- read_spd(&spd[2], 0x52, id_only);
- read_spd(&spd[3], 0x53, id_only);
-}