Attached patch removes unnecessary IRQ routing info (for ACPI, mptable etc needs to be fixed too). The devicetree.cb changes should reflect now the real board configuration. It has one 16x slot and 1x slot (GPP device 9) and GPP device a is onboard ethernet. The mainboard.c now presents the board name and

I removed the gpio asserts - I think those are not used here.

The pcie 1x slot works, the x1 card I have does not work in 16x slot, but in orig bios I cannot see it any slot, so it is kind of better.

The classic PCI slot works fine too. However it seems SATA has some issues.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 2 insertions, 44 deletions

diff --git a/src/mainboard/asrock/939a785gmh/dsdt.asl b/src/mainboard/asrock/939a785gmh/dsdt.asl
index b5f2952d00..f0621cbbe4 100644
--- a/src/mainboard/asrock/939a785gmh/dsdt.asl
+++ b/src/mainboard/asrock/939a785gmh/dsdt.asl
@@ -1064,10 +1064,6 @@ DefinitionBlock (
 		Method(_L18) {
 			/* DBGO("\\_GPE\\_L18\n") */
 			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 		}
 
@@ -1166,46 +1162,7 @@ DefinitionBlock (
 				} /* end _PRT */
 			} /* end PBR2 */
 
-			/* Dev3 is also an external GFX bridge, not used in Herring */
-
-			Device(PBR4) {
-				Name(_ADR, 0x00040000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS4) }   /* APIC mode */
-					Return (PS4)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR4 */
-
-			Device(PBR5) {
-				Name(_ADR, 0x00050000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS5) }   /* APIC mode */
-					Return (PS5)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR5 */
-
-			Device(PBR6) {
-				Name(_ADR, 0x00060000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS6) }   /* APIC mode */
-					Return (PS6)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR6 */
-
-			/* The onboard EtherNet chip */
-			Device(PBR7) {
-				Name(_ADR, 0x00070000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS7) }   /* APIC mode */
-					Return (PS7)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR7 */
-
-			/* GPP */
+			/* GPP x1 */
 			Device(PBR9) {
 				Name(_ADR, 0x00090000)
 				Name(_PRW, Package() {0x18, 4})
@@ -1215,6 +1172,7 @@ DefinitionBlock (
 				} /* end _PRT */
 			} /* end PBR9 */
 
+			/* ethernet */
 			Device(PBRa) {
 				Name(_ADR, 0x000A0000)
 				Name(_PRW, Package() {0x18, 4})