amd/geode_lx: Remove most boards

There is active work to convert remaining two boards,
PC Engines alix1c and alix2d, to EARLY_CBMEM_INIT.

Change-Id: I87e3963af7ef719e9fa2a8b0df34a896265905f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

10 files changed, 0 insertions, 371 deletions

diff --git a/src/mainboard/artecgroup/Kconfig b/src/mainboard/artecgroup/Kconfig
deleted file mode 100644
index 69804eec49..0000000000
--- a/src/mainboard/artecgroup/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-if VENDOR_ARTECGROUP
-
-choice
-	prompt "Mainboard model"
-
-source "src/mainboard/artecgroup/*/Kconfig.name"
-
-endchoice
-
-config MAINBOARD_VENDOR
-	string
-	default "Artec Group"
-
-endif # VENDOR_ARTECGROUP
-
-if VENDOR_ARTECGROUP || VENDOR_LINUTOP
-source "src/mainboard/artecgroup/*/Kconfig"
-endif # VENDOR_ARTECGROUP || VENDOR_LINUTOP
diff --git a/src/mainboard/artecgroup/dbe61/Kconfig b/src/mainboard/artecgroup/dbe61/Kconfig
deleted file mode 100644
index c512f7b28d..0000000000
--- a/src/mainboard/artecgroup/dbe61/Kconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-if BOARD_ARTECGROUP_DBE61 || BOARD_LINUTOP_LINUTOP1
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_AMD_GEODE_LX
-	select NORTHBRIDGE_AMD_LX
-	select SOUTHBRIDGE_AMD_CS5536
-	select HAVE_PIRQ_TABLE
-	select PIRQ_ROUTE
-	select UDELAY_TSC
-	select BOARD_ROMSIZE_KB_256
-	select POWER_BUTTON_FORCE_DISABLE
-
-config MAINBOARD_DIR
-	string
-	default artecgroup/dbe61
-
-if BOARD_ARTECGROUP_DBE61
-config MAINBOARD_PART_NUMBER
-	string
-	default "DBE61"
-endif
-
-config IRQ_SLOT_COUNT
-	int
-	default 3
-
-endif # BOARD_ARTECGROUP_DBE61
diff --git a/src/mainboard/artecgroup/dbe61/Kconfig.name b/src/mainboard/artecgroup/dbe61/Kconfig.name
deleted file mode 100644
index 7ebe0dfa87..0000000000
--- a/src/mainboard/artecgroup/dbe61/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ARTECGROUP_DBE61
-	bool "DBE61"
diff --git a/src/mainboard/artecgroup/dbe61/board_info.txt b/src/mainboard/artecgroup/dbe61/board_info.txt
deleted file mode 100644
index d059a75572..0000000000
--- a/src/mainboard/artecgroup/dbe61/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Category: settop
-Board URL: http://www.artecgroup.com/thincan/index.php?option=com_content&task=blogcategory&id=15&Itemid=34
-Flashrom support: y
diff --git a/src/mainboard/artecgroup/dbe61/cmos.layout b/src/mainboard/artecgroup/dbe61/cmos.layout
deleted file mode 100644
index b238a379d8..0000000000
--- a/src/mainboard/artecgroup/dbe61/cmos.layout
+++ /dev/null
@@ -1,28 +0,0 @@
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-456          1       e       1        ECC_memory
-1008         16      h       0        check_sum
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/artecgroup/dbe61/devicetree.cb b/src/mainboard/artecgroup/dbe61/devicetree.cb
deleted file mode 100644
index 2532885f28..0000000000
--- a/src/mainboard/artecgroup/dbe61/devicetree.cb
+++ /dev/null
@@ -1,41 +0,0 @@
-chip northbridge/amd/lx
-	device domain 0 on
-		device pci 1.0 on end	# Northbridge
-		device pci 1.1 on end	# Graphics
-		chip southbridge/amd/cs5536
-			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-			# SIRQ Mode = Active(Quiet) mode. Save power....
-			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
-			register "lpc_serirq_enable" = "0x00001002"
-			register "lpc_serirq_polarity" = "0x0000EFFD"
-			register "lpc_serirq_mode" = "1"
-			register "enable_gpio_int_route" = "0x0D0C0700"
-			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "0"	#0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "0"
-			register "com1_address" = "0x2F8"
-			register "com1_irq" = "3"
-			register "com2_enable" = "1"
-			register "com2_address" = "0x3F8"
-			register "com2_irq" = "4"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-			device pci b.0 on end	# Slot 3
-			device pci c.0 on end	# Slot 4
-			device pci d.0 on end	# Slot 1
-			device pci e.0 on end	# Slot 2
-			device pci f.0 on end	# ISA Bridge
-			device pci f.2 on end	# IDE Controller
-			device pci f.3 on end	# Audio
-			device pci f.4 on end	# OHCI
-			device pci f.5 on end	# EHCI
-		end
-	end
-	# APIC cluster is late CPU init.
-	device cpu_cluster 0 on
-		chip cpu/amd/geode_lx
-			device lapic 0 on end
-		end
-	end
-
-end
diff --git a/src/mainboard/artecgroup/dbe61/irq_tables.c b/src/mainboard/artecgroup/dbe61/irq_tables.c
deleted file mode 100644
index e1af4d7ff1..0000000000
--- a/src/mainboard/artecgroup/dbe61/irq_tables.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/pirq_routing.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-
-/* Platform IRQs */
-#define PIRQA 10
-#define PIRQB 11
-#define PIRQC 10
-#define PIRQD 11
-
-/* Map */
-#define M_PIRQA (1 << PIRQA)	/* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB)	/* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC)	/* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD)	/* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA	 1		/* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB	 2		/* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC	 3		/* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD	 4		/* Means Slot INTx# Connects To Chipset INTD# */
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,		/* u32 signature */
-	PIRQ_VERSION,		/* u16 version   */
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT,	/* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
-	0x00,			/* Where the interrupt router lies (bus) */
-	(0x0F << 3) | 0x0,	/* Where the interrupt router lies (dev) */
-	0x00,			/* IRQs devoted exclusively to PCI usage */
-	0x100B,			/* Vendor */
-	0x002B,			/* Device */
-	0,			/* Miniport data */
-	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
-	0x00,			/*      u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
-	{
-	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
-	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* CPU */
-	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
-	 {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* ethernet */
-	 }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/artecgroup/dbe61/mainboard.c b/src/mainboard/artecgroup/dbe61/mainboard.c
deleted file mode 100644
index 49d093ad6b..0000000000
--- a/src/mainboard/artecgroup/dbe61/mainboard.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright (C) 2007 Advanced Micro Devices
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License version 2 as
-* published by the Free Software Foundation.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-
-static void init_gpio(void)
-{
-	msr_t msr;
-	printk(BIOS_DEBUG, "Checking GPIO module...\n");
-
-	msr = rdmsr(MDD_LBAR_GPIO);
-	printk(BIOS_DEBUG, "DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo);
-}
-
-static void init(struct device *dev)
-{
-	/* BOARD-SPECIFIC INIT */
-	printk(BIOS_DEBUG, "ARTECGROUP DBE61 ENTER %s\n", __func__);
-
-	init_gpio();
-
-	printk(BIOS_DEBUG, "ARTECGROUP DBE61 EXIT %s\n", __func__);
-}
-
-static void mainboard_enable(struct device *dev)
-{
-	dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
deleted file mode 100644
index db08887299..0000000000
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <stdlib.h>
-#include <console/console.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-#include <southbridge/amd/cs5536/cs5536.h>
-#include "spd_table.h"
-#include <spd.h>
-#include <northbridge/amd/lx/raminit.h>
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
-	int i;
-
-	if (device == DIMM0) {
-		for (i = 0; i < (ARRAY_SIZE(spd_table)); i++) {
-			if (spd_table[i].address == address) {
-				return spd_table[i].data;
-			}
-		}
-	}
-
-	/* returns 0xFF on any failures */
-	return 0xFF;
-}
-
-#include "northbridge/amd/lx/pll_reset.c"
-#include "cpu/amd/geode_lx/cpureginit.c"
-#include "cpu/amd/geode_lx/syspreinit.c"
-#include "cpu/amd/geode_lx/msrinit.c"
-
-void asmlinkage mainboard_romstage_entry(unsigned long bist)
-{
-
-	msr_t msr;
-	static const struct mem_controller memctrl[] = {
-		{.channel0 = {DIMM0, DIMM1}}
-	};
-
-	SystemPreInit();
-	msr_init();
-
-	cs5536_early_setup();
-
-	/* NOTE: must do this AFTER the early_setup!
-	 * it is counting on some early MSR setup
-	 * for cs5536
-	 */
-	/* cs5536_disable_internal_uart	 disable them. Set them up now... */
-	cs5536_setup_onchipuart(2); /* dbe61 uses UART2 as COM1 */
-	/* set address to 3F8 */
-	msr = rdmsr(MDD_LEG_IO);
-	msr.lo |= 0x7 << 20;
-	wrmsr(MDD_LEG_IO, msr);
-
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	pll_reset();
-
-	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
-
-	sdram_initialize(1, memctrl);
-}
diff --git a/src/mainboard/artecgroup/dbe61/spd_table.h b/src/mainboard/artecgroup/dbe61/spd_table.h
deleted file mode 100644
index 6e052b3d88..0000000000
--- a/src/mainboard/artecgroup/dbe61/spd_table.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <spd.h>
-
-struct spd_entry {
-	unsigned int address;
-	unsigned int data;
-	};
-
-/* Save space by using a short list of SPD values used by Geode LX Memory init */
-/* 128MB */
-const struct spd_entry spd_table [] =
-{
-{SPD_MEMORY_TYPE,                     0x07}, /* (Fundamental) memory type */
-{SPD_NUM_ROWS,                        0x0D}, /* Number of row address bits */
-{SPD_NUM_COLUMNS,                     0x09}, /* Number of column address bits */
-{SPD_NUM_DIMM_BANKS,                  0x01}, /* Number of module rows (banks) */
-{SPD_MIN_CYCLE_TIME_AT_CAS_MAX,       0x50}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
-{SPD_REFRESH,                         0x82}, /* Refresh rate/type */
-{SPD_PRIMARY_SDRAM_WIDTH,             0x08}, /* SDRAM width (primary SDRAM) */
-{SPD_NUM_BANKS_PER_SDRAM,             0x04}, /* SDRAM device attributes, number of banks on SDRAM device */
-{SPD_ACCEPTABLE_CAS_LATENCIES,        0x1C}, /* SDRAM device attributes, CAS latency */
-{SPD_MODULE_ATTRIBUTES,               0x20}, /* SDRAM module attributes */
-{SPD_DEVICE_ATTRIBUTES_GENERAL,       0xC0}, /* SDRAM device attributes, general */
-{SPD_SDRAM_CYCLE_TIME_2ND,            0x60}, /* SDRAM cycle time (2nd highest CAS latency) */
-{SPD_SDRAM_CYCLE_TIME_3RD,            0x75}, /* SDRAM cycle time (3rd highest CAS latency) */
-{SPD_MIN_ROW_PRECHARGE_TIME,          0x3C}, /* Minimum row precharge time (Trp) */
-{SPD_MIN_ROWACTIVE_TO_ROWACTIVE,      0x28}, /* Minimum row active to row active (Trrd) */
-{SPD_MIN_RAS_TO_CAS_DELAY,            0x3C}, /* Minimum RAS to CAS delay (Trcd) */
-{SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY,   0x28}, /* Minimum RAS pulse width (Tras) */
-{SPD_DENSITY_OF_EACH_ROW_ON_MODULE,   0x20}, /* Density of each row on module */
-{SPD_CMD_SIGNAL_INPUT_HOLD_TIME,      0x60}, /* Command and address signal input hold time */
-{SPD_tRC,                             0x37}, /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
-{SPD_tRFC,                            0x46}  /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
-};