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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2017-07-25 12:29:59 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2017-07-27 13:13:02 +0000 |
| commit | 812f1783bbf437e57e7176ec8a2d29e478c27e92 (patch) | |
| tree | 08b8e00513fa120a1bf52506b305f77528afa01a /src/mainboard/artecgroup | |
| parent | 38b6100229e97db1441aab779d83e8b9a4c3e464 (diff) | |
siemens/mc_apl1: Select skip RAPL configuration
The mc_apl1 mainboard needs to disable the RAPL algorithm for a constant
power management of the processor package. An active RAPL algorithm
leads to negative effects with our real time software.
Change-Id: I09ca56a034fd3896a000e64cac35f12fb507a682
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/artecgroup')
0 files changed, 0 insertions, 0 deletions