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| author | Ronald G. Minnich <rminnich@gmail.com> | 2006-09-18 22:50:51 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-09-18 22:50:51 +0000 |
| commit | 2cf779d8d17ce2737ee1b49f6faecb7e76ac6b92 (patch) | |
| tree | 892c12a83d802ea9d05ff38e70aee43125a64619 /src/mainboard/artecgroup/dbe61 | |
| parent | 0740c31cff42e97ab16353d38a58b4bffdbb124d (diff) | |
fix old bug in the src/devices/pci_device.c
add devices for the lx and artecgroup/dbe61
point artecgroup at cs5536_lx as it is so different.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/artecgroup/dbe61')
| -rw-r--r-- | src/mainboard/artecgroup/dbe61/Config.lb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/artecgroup/dbe61/Config.lb b/src/mainboard/artecgroup/dbe61/Config.lb index 085685279b..b9d0e15f39 100644 --- a/src/mainboard/artecgroup/dbe61/Config.lb +++ b/src/mainboard/artecgroup/dbe61/Config.lb @@ -134,7 +134,7 @@ chip northbridge/amd/lx device pci_domain 0 on device pci 1.0 on end device pci 1.1 on end - chip southbridge/amd/cs5536 + chip southbridge/amd/cs5536_lx register "enable_gpio0_inta" = "1" register "enable_ide_nand_flash" = "1" register "enable_uarta" = "1" |