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authorNikolay Petukhov <nikolay.petukhov@gmail.com>2008-03-29 16:59:27 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2008-03-29 16:59:27 +0000
commit9c2255c66c20cd90f39cc08c1220d93222d5d580 (patch)
tree5856ba073775b3259a454545d7b6a3fda4c82824 /src/mainboard/artecgroup/dbe61
parent0e122af46553c394b1ac4c38dd83ab01c7c34a9c (diff)
Now coreboot performs IRQ routing for some boards.
You can see this by executing commands like this: grep -r pci_assign_irqs coreboot/src/* This basically AMD/LX based boards: pcengines/alix1c, digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800. Also for AMD/GX1 based boards need a patch [http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch] for the right IRQ setup. AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320, bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p. I have two ideas. 1. Delete duplicate code from AMD/LX based boards. 2. Add IRQ routing for AMD/GX1 boards in coreboot. The pirq.patch for IRQ routing logically consist from of two parts: First part of pirq.patch independent from type chipsets and assign IRQ for ever PCI device. It part based on AMD/LX write_pirq_routing_table() function. Second part of pirq.patch depends of type chipset and set PIRQx lines in interrupt router. This part supports only CS5530/5536 interrupt routers. IRQ routing functionality is included through PIRQ_ROUTE in Config.lb. Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on TeleVideo TC7020, see http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html. Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/artecgroup/dbe61')
-rw-r--r--src/mainboard/artecgroup/dbe61/Options.lb3
-rw-r--r--src/mainboard/artecgroup/dbe61/irq_tables.c41
2 files changed, 4 insertions, 40 deletions
diff --git a/src/mainboard/artecgroup/dbe61/Options.lb b/src/mainboard/artecgroup/dbe61/Options.lb
index d95f0a9bf7..9a35425463 100644
--- a/src/mainboard/artecgroup/dbe61/Options.lb
+++ b/src/mainboard/artecgroup/dbe61/Options.lb
@@ -48,6 +48,7 @@ uses CONFIG_VIDEO_MB
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -84,7 +85,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=3
-
+default PIRQ_ROUTE=1
#object irq_tables.o
##
diff --git a/src/mainboard/artecgroup/dbe61/irq_tables.c b/src/mainboard/artecgroup/dbe61/irq_tables.c
index 1c06e1d8c7..b42c4b514e 100644
--- a/src/mainboard/artecgroup/dbe61/irq_tables.c
+++ b/src/mainboard/artecgroup/dbe61/irq_tables.c
@@ -64,42 +64,5 @@ const struct irq_routing_table intel_irq_routing_table = {
unsigned long write_pirq_routing_table(unsigned long addr)
{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- uint16_t chipset_irq_map;
- uint32_t pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
-
- pirtable_end = copy_pirq_routing_table(addr);
-
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
- chipset_irq_map);
- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
-
- pirq_tbl = (struct irq_routing_table *)(addr);
- num_entries = (pirq_tbl->size - 32) / 16;
-
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
- printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
- pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
- for (j = 0; j < 4; j++) {
- printk_debug("INT: %c bitmap: %x ", 'A' + j,
- pirq_tbl->slots[i].irq[j].bitmap);
- for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in bitmap to IRQ#. */
- pirq[j] = k;
- printk_debug("PIRQ: %d\n", k);
- }
-
- /* Bus, device, slots IRQs for {A,B,C,D}. */
- pci_assign_irqs(pirq_tbl->slots[i].bus,
- pirq_tbl->slots[i].devfn >> 3, pirq);
- }
-
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
-} \ No newline at end of file
+ return copy_pirq_routing_table(addr);
+}