diff options
| author | Indrek Kruusa <indrek.kruusa@artecdesign.ee> | 2006-08-03 16:48:18 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2006-08-03 16:48:18 +0000 |
| commit | 8e3464109e47945b1a4d7e3dd0c6e291593de70a (patch) | |
| tree | 03493e297dc332c8c7613303eb874e12830e0a5a /src/mainboard/artecgroup/dbe61/Options.lb | |
| parent | 8ad7c06535694959952b7d64a9649cb9534abd2a (diff) | |
Changelog:
* src/cpu/amd/model_lx/model_lx_init.c
L2 cache initialization removed (moved to northbridge.c)
* src/include/cpu/amd/lxdef.h
more checked values
* src/northbridge/amd/lx/northbridge.c
L2 cache initialization added
cpubug() commented out
* src/northbridge/amd/lx/raminit.c
empty function sdram_set_registers() is in use, don't remove
* src/mainboard/artecgroup/dbe61/Config.lb
irqmap changes
* src/mainboard/artecgroup/dbe61/irq_tables.c
tentative changes to irq table (currently not in use)
* src/mainboard/artecgroup/dbe61/mainboard.c
irq assigned manually to NIC
* src/mainboard/artecgroup/dbe61/Options.lb
gcc 4.0 is OK
* targets/artecgroup/dbe61/Config.lb
64K for VSA is OK at moment
Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee>
Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/artecgroup/dbe61/Options.lb')
| -rw-r--r-- | src/mainboard/artecgroup/dbe61/Options.lb | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mainboard/artecgroup/dbe61/Options.lb b/src/mainboard/artecgroup/dbe61/Options.lb index fccf121786..1112fcee2c 100644 --- a/src/mainboard/artecgroup/dbe61/Options.lb +++ b/src/mainboard/artecgroup/dbe61/Options.lb @@ -71,8 +71,9 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=2 +default HAVE_PIRQ_TABLE=0 +default IRQ_SLOT_COUNT=6 + #object irq_tables.o ## @@ -112,8 +113,8 @@ default CONFIG_ROM_STREAM = 1 ## The default compiler ## default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc-3.4 -m32" -default HOSTCC="gcc-3.4" +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" ## ## The Serial Console |