diff options
| author | Naresh Solanki <naresh.solanki@9elements.com> | 2023-11-17 02:21:57 +0530 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-10-16 15:30:31 +0000 |
| commit | 6d1dbe12d2f869388ddb51e0cef7bf30ce80b255 (patch) | |
| tree | d6db121cfc41e5d750e00dc80d3cfadda482ea15 /src/mainboard/arm/rdn2/memlayout.ld | |
| parent | f6ecfbc12b4d4c02cc33b1d854ec9a473fe3f2fb (diff) | |
mb/arm/rdn2: Add support for Arm Neoverse N2
Add support for Arm Neoverse N2 Reference design.
Based on Arm Neoverse N2 reference design
Revision: Release D
TEST=Build Arm Neoverse N2 & make sure there is no error.
Change-Id: I17908d3ce773d4a88924bafb1d0e9e2a043c7fbc
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/arm/rdn2/memlayout.ld')
| -rw-r--r-- | src/mainboard/arm/rdn2/memlayout.ld | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/mainboard/arm/rdn2/memlayout.ld b/src/mainboard/arm/rdn2/memlayout.ld new file mode 100644 index 0000000000..de7aad5086 --- /dev/null +++ b/src/mainboard/arm/rdn2/memlayout.ld @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* + * Memory map for Neoverse N2 + * See Technical Reference: Table 5-2: FVP board peripherals + */ +SECTIONS +{ + REGION(flash, 0x8000000, CONFIG_ROM_SIZE, 8) + + REGION(dev_mem, 0x0c010000, 2M, 8) + DRAM_START(0x80000000) + BOOTBLOCK(0xe0000000, 64K) + STACK(0xe0010000, 64K) + CBFS_MCACHE(0xe0020000, 8K) + FMAP_CACHE(0xe0022000 , 4K) + TIMESTAMP(0xe0023000, 4K) + ROMSTAGE(0xe0024000, 128K) + TTB(0xe0060000, 128K) + RAMSTAGE(0xe00a0000, 16M) + REGION(fdt_pointer, 0xe10a0000, ARCH_POINTER_ALIGN_SIZE, ARCH_POINTER_ALIGN_SIZE) + + POSTRAM_CBFS_CACHE(0xe11f0000, 1M) +} |