diff options
| author | Naresh Solanki <naresh.solanki@9elements.com> | 2023-11-17 02:21:57 +0530 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-10-16 15:30:31 +0000 |
| commit | 6d1dbe12d2f869388ddb51e0cef7bf30ce80b255 (patch) | |
| tree | d6db121cfc41e5d750e00dc80d3cfadda482ea15 /src/mainboard/arm/rdn2/bootblock.c | |
| parent | f6ecfbc12b4d4c02cc33b1d854ec9a473fe3f2fb (diff) | |
mb/arm/rdn2: Add support for Arm Neoverse N2
Add support for Arm Neoverse N2 Reference design.
Based on Arm Neoverse N2 reference design
Revision: Release D
TEST=Build Arm Neoverse N2 & make sure there is no error.
Change-Id: I17908d3ce773d4a88924bafb1d0e9e2a043c7fbc
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/arm/rdn2/bootblock.c')
| -rw-r--r-- | src/mainboard/arm/rdn2/bootblock.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/src/mainboard/arm/rdn2/bootblock.c b/src/mainboard/arm/rdn2/bootblock.c new file mode 100644 index 0000000000..5b59e7e033 --- /dev/null +++ b/src/mainboard/arm/rdn2/bootblock.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/mmu.h> +#include <bootblock_common.h> +#include <console/console.h> +#include <mainboard/addressmap.h> +#include <symbols.h> + +DECLARE_REGION(dev_mem) + +void bootblock_mainboard_init(void) +{ + mmu_init(); + + /* NOR Flash 0 */ + mmu_config_range((void *)RDN2_FLASH_BASE, (uintptr_t)RDN2_FLASH_SIZE, + MA_MEM | MA_RO | MA_MEM_NC); + + /* device memory */ + mmu_config_range(_dev_mem, _dram - _dev_mem, MA_DEV | MA_RW); + + /* Set a dummy value for DRAM. ramstage should update the mapping. */ + mmu_config_range(_dram, ((size_t) 2 * GiB) - 16*MiB, MA_MEM | MA_RW); + + mmu_config_range((void *)RDN2_DRAM2_BASE, RDN2_DRAM2_SIZE, MA_MEM | MA_RW); + + mmu_config_range(_ttb, REGION_SIZE(ttb), MA_MEM | MA_S | MA_RW); + + mmu_config_range(_stack, REGION_SIZE(stack), MA_MEM | MA_S | MA_RW); + mmu_config_range(_cbfs_mcache, REGION_SIZE(cbfs_mcache), MA_MEM | MA_S | MA_RW); + mmu_config_range(_fmap_cache, REGION_SIZE(fmap_cache), MA_MEM | MA_S | MA_RW); + mmu_config_range(_timestamp, REGION_SIZE(timestamp), MA_MEM | MA_S | MA_RW); + + mmu_config_range((void *)CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, + MA_DEV | MA_RW); + mmu_enable(); +} |