more breakage, thanks to Ron

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 189 insertions, 320 deletions

diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb
index f8091bdbe8..c5ed005f80 100644
--- a/src/mainboard/arima/hdama/Config.lb
+++ b/src/mainboard/arima/hdama/Config.lb
@@ -1,127 +1,3 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-
-
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE=524288
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default HAVE_HARD_RESET=1
-
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default HAVE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=1
-
-##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
-##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default MAINBOARD_PART_NUMBER="HDAMA"
-default MAINBOARD_VENDOR="ARIMA"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
-
-###
-### LinuxBIOS layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-
 ##
 ## Compute the location and size of where this firmware image
 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
@@ -157,203 +33,72 @@ default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
 default XIP_ROM_SIZE=65536
 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
 
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c" 
-	action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
-end
-
-makerule ./failover.inc
-	depends "./failover.E ./romcc"
-	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
-end
-
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h " 
-	action	"$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
-end
-makerule ./auto.inc 
-	depends "./auto.E ./romcc"
-	action	"./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
-end
-
-##
-## Build our 16 bit and 32 bit linuxBIOS entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where linuxBIOS is entered)
-##
-if USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of linuxBIOS startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-northbridge amd/amdk8 "mc0"
-	pnp cf8.0
-	northbridge amd/amdk8 "mc1" link 0
-		pci 0:19.0
-		pci 0:19.0
-		pci 0:19.0
-		pci 0:19.1
-		pci 0:19.2
-		pci 0:19.3
-	end
-	pci 1:18.0
-	southbridge amd/amd8131 "amd8131" link 1
-		pci 0:0.0
-		pci 0:0.1
-		pci 0:1.0
-		pci 0:1.1
-	end
-	southbridge amd/amd8111 "amd8111" link 1
-		pci 0:0.0
-		pci 0:1.0 on
-		superio NSC/pc87360 link 1
-			pnp 2e.0 off  # Floppy 
-				 io 0x60 = 0x3f0
-				irq 0x70 = 6
-				drq 0x74 = 2
-			pnp 2e.1 off  # Parallel Port
-				 io 0x60 = 0x378
-				irq 0x70 = 7
-			pnp 2e.2 off # Com 2
-				 io 0x60 = 0x2f8
-				irq 0x70 = 3
-			pnp 2e.3 on  # Com 1
-				 io 0x60 = 0x3f8
-				irq 0x70 = 4
-			pnp 2e.4 off # SWC
-			pnp 2e.5 off # Mouse
-			pnp 2e.6 on  # Keyboard
-				 io 0x60 = 0x60
-				 io 0x62 = 0x64
-				irq 0x70 = 1
-			pnp 2e.7 off # GPIO
-			pnp 2e.8 off # ACB
-			pnp 2e.9 off # FSCM
-			pnp 2e.a off # WDT  
-		end
-		pci 0:1.1 on
-		pci 0:1.2 on 
-		pci 0:1.3 on # ACPI/SMBUS
-			chip drivers/generic/generic link 4 
-				#phillips pca9545 smbus mux
-				i2c 70
-					# analog_devices adm1026	
-					chip drivers/generic/generic link 0
-						i2c 2c
-					end
-				i2c 70
-				i2c 70
-				i2c 70
-			end
-			chip drivers/generic/generic link 4 #dimm 0-0-0
-				i2c 50
+# sample config for arima/hdama
+chip northbridge/amd/amdk8
+	print "HI MOM!\n"
+	device pnp cf8.0 on					# cf8 config
+	print "HI MOM!\n"
+		device pci 18.0 on				#  northbridge 
+	print "HI MOM!\n"
+			#  devices on link 0, link 0 == LDT 0 
+			chip southbridge/amd/amd8131
+			print "SOUTH\n"
+				# the on/off keyword is mandatory
+				device pci 0.0 on end
+			print "SOUTH2\n"
+				device pci 0.1 on end
+			print "SOUTH3\n"
+				device pci 1.0 on end
+			print "SOUTH4\n"
+				device pci 1.1 on end
 			end
-			chip drivers/generic/generic link 4 #dimm 0-0-1
-				i2c 51
-			end 
-			chip drivers/generic/generic link 4 #dimm 0-1-0
-				i2c 52
-			end 
-			chip drivers/generic/generic link 4 #dimm 0-1-1
-				i2c 53
-			end 
-			chip drivers/generic/generic link 4 #dimm 1-0-0
-				i2c 54
+			chip southbridge/amd/amd8111
+				print "NEXT SOUTH\n"
+				# this "device pci 0.0" is the parent the next one
+				# PCI bridge
+				device pci 0.0 on
+					# this "device pci 0.0" is a child of the
+					# previous one
+					# devices behind the bridge
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 0.2 on end
+					# the device statement can span across multiple
+					# lines too
+					device pci 1.0
+						off
+					end
+				end
+				device pci 1.0 on
+					chip superio/NSC/pc87360
+						device pnp 2e.3 on
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end 
+					end
+				end
+				device pci 1.1 on end
+				device pci 1.2 off end
+				device pci 1.3 off end
+				device pci 1.5 on end
+				device pci 1.6 on end
 			end
-			chip drivers/generic/generic link 4 #dimm 1-0-1
-				i2c 55
-			end 
-			chip drivers/generic/generic link 4 #dimm 1-1-0
-				i2c 56
-			end 
-			chip drivers/generic/generic link 4 #dimm 1-1-1
-				i2c 57
-			end 
-		pci 0:1.5 off
-		pci 0:1.6 off
-		pci 1:0.0 on
-		pci 1:0.1 on
-		pci 1:0.2 on
-		pci 1:1.0 off
-	end
-	pci 1:18.0
-	pci 1:18.0
-	pci 1:18.1
-	pci 1:18.2
-	pci 1:18.3
-end
-
-
-cpu amd/socket_940 "cpu0" link 1
-	apic 0
-end
-
-cpu amd/socket_940 "cpu1" link 1
-	apic 1
+		end #  device pci 18.0 
+		device pci 18.0 on
+			#  some non-existence devices on link 1 
+		end
+		device pci 18.0 on
+			#  some non-existence devices on link 2 
+		end
+		device pci 18.1
+			#  empty 
+		end
+		device pci 18.2
+			#  empty 
+		end
+		device pci 18.3
+			#  empty 
+		end
+	end #  device pnp 
 end
 
diff --git a/src/mainboard/arima/hdama/Options.lb b/src/mainboard/arima/hdama/Options.lb
new file mode 100644
index 0000000000..f2c2dba2bb
--- /dev/null
+++ b/src/mainboard/arima/hdama/Options.lb
@@ -0,0 +1,124 @@
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses HARD_RESET_BUS
+uses HARD_RESET_DEVICE
+uses HARD_RESET_FUNCTION
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_STREAM_START
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD
+uses LINUXBIOS_EXTRA_VERSION
+uses _RAMBASE
+
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+default ROM_SIZE=524288
+
+###
+### Build options
+###
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+default HARD_RESET_BUS=1
+default HARD_RESET_DEVICE=4
+default HARD_RESET_FUNCTION=0
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=9
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
+
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=2
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default MAINBOARD_PART_NUMBER="HDAMA"
+default MAINBOARD_VENDOR="ARIMA"
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x4000
+
+##
+## Only use the option table in a normal image
+##
+default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default _RAMBASE=0x00004000
+end