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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-12-29 11:32:27 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-04-28 07:59:13 +0200
commitb85a87b7d6f9f12d5c71c32741c8af731ed6be7e (patch)
tree67553a9c683557ead346dc1c7b155d3eac475090 /src/mainboard/apple
parent189f3ba974df8f1b305cfa421a151fe069fc1a6f (diff)
intel SMI handlers: Refactor GPI SMI/SCI routing
Move the GPI interrupt routing selection between SMI/SCI from mainboards to southbridge. There is speculation if this is all just legacy APM stuff that could be removed with a followup. Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7967 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Diffstat (limited to 'src/mainboard/apple')
-rw-r--r--src/mainboard/apple/macbook21/smihandler.c20
1 files changed, 2 insertions, 18 deletions
diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c
index f90bb38336..5c6cd443d9 100644
--- a/src/mainboard/apple/macbook21/smihandler.c
+++ b/src/mainboard/apple/macbook21/smihandler.c
@@ -60,30 +60,14 @@ int mainboard_io_trap_handler(int smif)
int mainboard_smi_apmc(u8 data)
{
- u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
- u8 tmp;
-
- printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data);
-
- if (!pmbase)
- return 0;
-
switch(data) {
case APM_CNT_ACPI_ENABLE:
/* route H8SCI to SCI */
- outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
- tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
- tmp &= ~0x03;
- tmp |= 0x02;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
break;
case APM_CNT_ACPI_DISABLE:
/* route H8SCI# to SMI */
- outw(inw(pmbase + ALT_GP_SMI_EN) | (1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
- tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
- tmp &= ~0x03;
- tmp |= 0x01;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
break;
default:
break;