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authorVladimir Serbinenko <phcoder@gmail.com>2015-05-29 22:07:29 +0200
committerVladimir Serbinenko <phcoder@gmail.com>2015-10-11 10:05:17 +0000
commit55f3e2fd00f6aaf3fc58fc6f91197e3a7793afc6 (patch)
tree78601fa30b7b0c0f1c6f5848c99a136c175fbcdd /src/mainboard/apple/macbookair4_2/early_southbridge.c
parent52262662daa88fa43272a6329dfa70489fbf2240 (diff)
Autogenerate MacBookAir4,2
Just ran autoport on the data from MacBookAir4,2 Change-Id: Iba2a56a6846d81d29e6b090a9a31253ce240914d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/11840 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/apple/macbookair4_2/early_southbridge.c')
-rw-r--r--src/mainboard/apple/macbookair4_2/early_southbridge.c61
1 files changed, 61 insertions, 0 deletions
diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c
new file mode 100644
index 0000000000..e1b667d54d
--- /dev/null
+++ b/src/mainboard/apple/macbookair4_2/early_southbridge.c
@@ -0,0 +1,61 @@
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit_native.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+
+void pch_enable_lpc(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
+}
+
+void rcba_config(void)
+{
+ /* Disable devices. */
+ RCBA32(0x3414) = 0x00000020;
+ RCBA32(0x3418) = 0x1ffc0ee3;
+
+}
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+};
+
+/* FIXME: Put proper SPD map here. */
+void mainboard_get_spd(spd_raw_data *spd)
+{
+ read_spd(&spd[0], 0x50);
+ read_spd(&spd[1], 0x51);
+ read_spd(&spd[2], 0x52);
+ read_spd(&spd[3], 0x53);
+}