diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-09-18 20:15:45 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-02 19:06:55 +0200 |
| commit | 5db043f0d6ddcae38b8addde1c8b3466265fa823 (patch) | |
| tree | 683697b23eb2c0819369520077a5ebfde86d9917 /src/mainboard/apple/macbook21 | |
| parent | a90c7859d9c7cec337a8148e186344a1ca152b40 (diff) | |
apple/imac52: add mainboard
Add Imac5,2 based on macbook2,1 port.
Change-Id: I34c8313c32920b02a2b964d8718e5b2b6b5a6820
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16638
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/apple/macbook21')
| -rw-r--r-- | src/mainboard/apple/macbook21/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/apple/macbook21/hda_verb.c | 38 | ||||
| -rw-r--r-- | src/mainboard/apple/macbook21/romstage.c | 14 |
3 files changed, 52 insertions, 2 deletions
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index e653c08892..ebf3954dac 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -1,4 +1,4 @@ -if BOARD_APPLE_MACBOOK11 || BOARD_APPLE_MACBOOK21 +if BOARD_APPLE_MACBOOK11 || BOARD_APPLE_MACBOOK21 || BOARD_APPLE_IMAC52 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y diff --git a/src/mainboard/apple/macbook21/hda_verb.c b/src/mainboard/apple/macbook21/hda_verb.c index c048481ff2..e0fc92edbd 100644 --- a/src/mainboard/apple/macbook21/hda_verb.c +++ b/src/mainboard/apple/macbook21/hda_verb.c @@ -19,6 +19,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x83847680, /* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */ +#if CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21 0x106b2200, /* Subsystem ID */ 0x0000000B, /* Number of 4 dword sets */ @@ -54,6 +55,43 @@ const u32 cim_verb_data[] = { /* NID 0x1B. */ AZALIA_PIN_CFG(0x0, 0x1B, 0x400000FB), +#else /* CONFIG_BOARD_APPLE_IMAC52 */ + 0x106b0f00, /* Subsystem ID */ + 0x0000000b, /* Number of 4 dword sets */ + + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106b0f00), + + /* NID 0x0A. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x012be032), + + /* NID 0x0B. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x90afe111), + + /* NID 0x0C. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x9017e131), + + /* NID 0x0D. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x4080e10f), + + /* NID 0x0E. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x40f0e00f), + + /* NID 0x0F */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x018be021), + + /* NID 0x10 */ + AZALIA_PIN_CFG(0x0, 0x10, 0x114bf033), + + /* NID 0x11 */ + AZALIA_PIN_CFG(0x0, 0x11, 0x11cbc022), + + /* NID 0x15 */ + AZALIA_PIN_CFG(0x0, 0x15, 0x4080e10f), + + /* NID 0x1B. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x4080e10f), +#endif }; diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 4d49e89326..695f1cd291 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -62,7 +62,7 @@ void setup_ich7_gpios(void) * 39: PLANARID3 * 48: FWH_TBL# */ - +#if (CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21) outl(0x1f40f7e2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ outl(0xfcc06bdf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ @@ -73,6 +73,18 @@ void setup_ich7_gpios(void) outl(0x000100c0, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +#else /* CONFIG_BOARD_APPLE_IMAC52 */ + outl(0x1f40f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xfcc06bff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x00000082, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000100c8, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +#endif } static void ich7_enable_lpc(void) |