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| author | Cliff Huang <cliff.huang@intel.com> | 2024-08-19 10:44:06 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-09-02 03:53:50 +0000 |
| commit | 105b5d376fa0adc4212f953756c7cb11252836ed (patch) | |
| tree | e7e6a9b63c79768df3f74b26ddfc6fe10b56f094 /src/mainboard/aopen/dxplplusu/devicetree.cb | |
| parent | f51885d370f4af0a03cec4e6ea85d99d81575fc4 (diff) | |
soc/intel/common/gpio: support 16-bit CPU Port ID
- Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID.
- Change cpu_port field to 16-bit width if the Kconfig is set.
BUG=none
TEST=boot to OS and use iotools to read the registers that use 16-bit
port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group
ID field. The bit 15:8 of the returned port ID value should be 0xF2
instead of zero.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83981
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/aopen/dxplplusu/devicetree.cb')
0 files changed, 0 insertions, 0 deletions