diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-07 17:35:50 +0200 |
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committer | Martin Roth <martinroth@google.com> | 2016-10-11 23:32:53 +0200 |
commit | 46829869c8d96457042601ff1dfba2a75ba79db1 (patch) | |
tree | ce0266461a6684b1ccad6d29269e4ed54d188137 /src/mainboard/aopen/dxplplusu/bus.h | |
parent | 626f8c84405fc4a16e72fc3e4dc829ca106ea2cf (diff) |
mainboard/aopen: Use C89 comments style & remove commented code
Change-Id: I0014fc030888d71f7951c97bccc7cef0e1c45186
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16922
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/aopen/dxplplusu/bus.h')
-rw-r--r-- | src/mainboard/aopen/dxplplusu/bus.h | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/src/mainboard/aopen/dxplplusu/bus.h b/src/mainboard/aopen/dxplplusu/bus.h index 96321c9fc4..965b8b78b0 100644 --- a/src/mainboard/aopen/dxplplusu/bus.h +++ b/src/mainboard/aopen/dxplplusu/bus.h @@ -16,23 +16,24 @@ #ifndef DXPLPLUSU_BUS_H_INCLUDED #define DXPLPLUSU_BUS_H_INCLUDED -// These were determined by seeing how coreboot enumerates the various -// PCI (and PCI-like) buses on the board. +/* These were determined by seeing how coreboot enumerates the various + * PCI (and PCI-like) buses on the board. + */ #define PCI_BUS_ROOT 0 -#define PCI_BUS_AGP 1 // AGP -#define PCI_BUS_E7501_HI_B 2 // P64H2#1 -#define PCI_BUS_P64H2_B 3 // P64H2#1 bus B -#define PCI_BUS_P64H2_A 4 // P64H2#1 bus A -#define PCI_BUS_ICH4 5 // ICH4 +#define PCI_BUS_AGP 1 /* AGP */ +#define PCI_BUS_E7501_HI_B 2 /* P64H2#1 */ +#define PCI_BUS_P64H2_B 3 /* P64H2#1 bus B */ +#define PCI_BUS_P64H2_A 4 /* P64H2#1 bus A */ +#define PCI_BUS_ICH4 5 /* ICH4 */ -// IOAPIC addresses determined by coreboot enumeration. -// Someday add functions to get APIC IDs and versions from the chips themselves. +/* IOAPIC addresses determined by coreboot enumeration. */ +/* Someday add functions to get APIC IDs and versions from the chips themselves. */ #define IOAPIC_ICH4 2 -#define IOAPIC_P64H2_BUS_B 3 // IOAPIC 3 at 02:1c.0 MBAR = fe300000 DataAddr = fe300010 -#define IOAPIC_P64H2_BUS_A 4 // IOAPIC 4 at 02:1e.0 MBAR = fe301000 DataAddr = fe301010 +#define IOAPIC_P64H2_BUS_B 3 /* IOAPIC 3 at 02:1c.0 MBAR = fe300000 DataAddr = fe300010 */ +#define IOAPIC_P64H2_BUS_A 4 /* IOAPIC 4 at 02:1e.0 MBAR = fe301000 DataAddr = fe301010 */ -#define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-4 and P64-H2 +#define INTEL_IOAPIC_NUM_INTERRUPTS 24 /* Both ICH-4 and P64-H2 */ #endif |