Add support for A-Open DXPL Plus-U motherboard

This is an old (pre-2005) entry-level server mainboard. The code
is adapted from mainboard/intel/xe7501devkit.

Featured chips:
 - Dual socket604
 - E7505 northbridge
 - 82801DB southbridge (with EHCI debug port)
 - 82870p2 PCI-X bridge
 - LPC47M102S-MC super-io
 - 512kB FWH flash (flashrom does the job well)

What works:
 - Dual-Xeon P4/HT boot with microcode update
 - RAM: registered ECC DDR266 in dual-channel
 - PCI-X slot interrupts with ACPI and I/O apic
 - On-board PCI-X GbE and SCSI
 - ACPI power-off and wakeup with PME#

Notes :
 - Current ACPI is more or less a mess
 - Interrupts do not route correctly with PIRQ
 - MP-table is not implemented
 - Issues with reboots remain (cold and warm)
 - Many superio devices are disabled by default
 - Audio codec is not investigated

Change-Id: I02d18c83f485a09ada65dde03bcc86e9163f2011
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/303
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

1 files changed, 42 insertions, 0 deletions

diff --git a/src/mainboard/aopen/dxplplusu/bus.h b/src/mainboard/aopen/dxplplusu/bus.h
new file mode 100644
index 0000000000..7cb188d266
--- /dev/null
+++ b/src/mainboard/aopen/dxplplusu/bus.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef DXPLPLUSU_BUS_H_INCLUDED
+#define DXPLPLUSU_BUS_H_INCLUDED
+
+// These were determined by seeing how coreboot enumerates the various
+// PCI (and PCI-like) buses on the board.
+
+#define PCI_BUS_ROOT		0
+#define PCI_BUS_AGP		1	// AGP
+#define PCI_BUS_E7501_HI_B	2	// P64H2#1
+#define PCI_BUS_P64H2_B		3	// P64H2#1 bus B
+#define PCI_BUS_P64H2_A		4	// P64H2#1 bus A
+#define PCI_BUS_ICH4		5	// ICH4
+
+// IOAPIC addresses determined by coreboot enumeration.
+// Someday add functions to get APIC IDs and versions from the chips themselves.
+
+#define IOAPIC_ICH4		2
+#define IOAPIC_P64H2_BUS_B	3	// IOAPIC 3 at 02:1c.0  MBAR = fe300000 DataAddr = fe300010
+#define IOAPIC_P64H2_BUS_A	4	// IOAPIC 4 at 02:1e.0  MBAR = fe301000 DataAddr = fe301010
+
+#define INTEL_IOAPIC_NUM_INTERRUPTS 	24	// Both ICH-4 and P64-H2
+
+#endif