mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)

AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with
two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4-3200
SODIMM slot up to 32GB. It also comes with 2x 2.5Gb Intel NICs,
Intel AX200 WiFi + BT and USB-C Alt-DP Power Delivery.

Working:
- DDR4 RAM (tested with Crucial 16GB 3200MHz CL22)
- Automatic FAN control (IT8613E Super I/O)
- M.2 NVME slot
- 2x SATA ports (Issue on 3.5" HDD, see below)
- USB 2.0 ports
- USB 3.0 ports
- USB-C port with Alt-DP and PD
- HDMI / DisplayPort ports
- 2x 2.5Gb NICs
- WiFi + BT
- MicroSD card reader
- ASPM (Unavailable on stock)
- Linux (Arch Linux, kernel 6.8.7-arch1-1) UEFI booting with EDK2
- Windows 10 UEFI booting with EDK2

Broken:
- Power button (OFF->ON broken, ON->OFF works)
- 3.5" SATA HDDs (Detected only after reboot)

Untested:
- Internal audio
- S3

My motivation for doing this port is enabling ASPM, as it makes a
great difference on idle power consumption (from 8.4W to 5W measured
from the wall).

The last remaining annoyance of this port is the power button not
working. I spent a few hours double checking the Super I/O registers but
then I gave up. A workaround for this is to use the "ON after power
loss" feature and reconnect the power cord to turn on the board.
It's not a big problem for a NAS that will stay ON 24/7.
Any hint on the power button or 3.5" HDD issue is welcome.

VBT extracted from vendor UEFI firmware version 1AXFE 0.01 x64
(Build date and time 11/29/2023 10:57:44)
Compiled with FSP GOP video initialization, using IFD descriptor
and ME blob extracted from vendor UEFI firmware (see above).

The board can be flashed externally using a 1.8V adapter, I used a
CH341a modded for 3.3V I/O. Internal flashing works, as flash is
not read/write protected.

Patchset 5: Re-enabled dptf, added default options to Kconfig.
Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works
Patchset 8: Fixed microSD card reader
Patchset 13: Change Super I/O Fan configuration to reduce fan noise

Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5
Signed-off-by: Federico Amedeo Izzo <federico@izzo.pro>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82010
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

10 files changed, 704 insertions, 0 deletions

diff --git a/src/mainboard/aoostar/wtr_r1/Kconfig b/src/mainboard/aoostar/wtr_r1/Kconfig
new file mode 100644
index 0000000000..fd7ddbf685
--- /dev/null
+++ b/src/mainboard/aoostar/wtr_r1/Kconfig
@@ -0,0 +1,47 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_AOOSTAR_WTR_R1
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_GENERIC
+	select DRIVERS_INTEL_DPTF
+	select DRIVERS_SPI_ACPI
+	select DRIVERS_USB_ACPI
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_GMA_HAVE_VBT
+	select SOC_INTEL_COMMON_BLOCK_IPU
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SUPERIO_ITE_IT8613E
+	select DRIVERS_UART_8250IO
+	select USE_LEGACY_8254_TIMER
+	select SOC_INTEL_ALDERLAKE_PCH_N
+
+config MAINBOARD_DIR
+	default "aoostar/wtr_r1"
+
+config MAINBOARD_PART_NUMBER
+	default "WTR R1"
+
+config MAINBOARD_FAMILY
+	string
+	default "AOOSTAR_WTR_R1"
+
+config PCIEXP_ASPM
+	default y
+
+# Setting this makes NVMe SSD not work
+config PCIEXP_L1_SUB_STATE
+	default n
+
+# Setting this makes 2.5Gb NICs not work
+config PCIEXP_CLK_PM
+	default n
+
+# This platform has limited means to display POST codes
+config NO_POST
+	default y
+
+endif #BOARD_AOOSTAR_WTR_R1
diff --git a/src/mainboard/aoostar/wtr_r1/Kconfig.name b/src/mainboard/aoostar/wtr_r1/Kconfig.name
new file mode 100644
index 0000000000..45bfdecf75
--- /dev/null
+++ b/src/mainboard/aoostar/wtr_r1/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_AOOSTAR_WTR_R1
+	bool "WTR R1"
diff --git a/src/mainboard/aoostar/wtr_r1/Makefile.mk b/src/mainboard/aoostar/wtr_r1/Makefile.mk
new file mode 100644
index 0000000000..72915efea8
--- /dev/null
+++ b/src/mainboard/aoostar/wtr_r1/Makefile.mk
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+romstage-y += romstage_fsp_params.c
diff --git a/src/mainboard/aoostar/wtr_r1/board_info.txt b/src/mainboard/aoostar/wtr_r1/board_info.txt
new file mode 100644
index 0000000000..363cd5352f
--- /dev/null
+++ b/src/mainboard/aoostar/wtr_r1/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: AOOSTAR
+Board name: WTR R1
+Board URL: https://aoostar.com/products/aoostar-r1-2bay-nas-intel-n100-mini-pc-with-w11-pro-lpddr4-16gb-ram-512gb-ssd
+Category: mini
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2023
diff --git a/src/mainboard/aoostar/wtr_r1/bootblock.c b/src/mainboard/aoostar/wtr_r1/bootblock.c
new file mode 100644
index 0000000000..d494f9ad17
--- /dev/null
+++ b/src/mainboard/aoostar/wtr_r1/bootblock.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8613e/it8613e.h>
+
+#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO)
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Set up GPIOs on Super I/O. */
+	ite_reg_write(GPIO_DEV, 0x25, 0x01); // Enable Pin GP10
+	ite_reg_write(GPIO_DEV, 0x27, 0x02); // Enable Pin GP31
+	ite_reg_write(GPIO_DEV, 0x28, 0x01); // Enable Pin GP40
+	ite_reg_write(GPIO_DEV, 0x29, 0x01); // Enable Pin GP50
+	ite_reg_write(GPIO_DEV, 0x2c, 0x41); // Internal Voltage Divider for ACC3
+	ite_reg_write(GPIO_DEV, 0xbc, 0xc0); // GP56, GP57 Internal pullup
+	ite_reg_write(GPIO_DEV, 0xbd, 0x03); // GP60, GP61 Internal pullup
+	ite_reg_write(GPIO_DEV, 0xc3, 0x41); // GP40, GP46 Simple I/O function
+	ite_set_3vsbsw(GPIO_DEV, true);
+	ite_delay_pwrgd3(GPIO_DEV);
+}
+
+void bootblock_mainboard_init(void)
+{
+}
diff --git a/src/mainboard/aoostar/wtr_r1/data.vbt b/src/mainboard/aoostar/wtr_r1/data.vbt
new file mode 100644
index 0000000000..f25d9d9e0f
--- /dev/null
+++ b/src/mainboard/aoostar/wtr_r1/data.vbt
diff --git a/src/mainboard/aoostar/wtr_r1/devicetree.cb b/src/mainboard/aoostar/wtr_r1/devicetree.cb
new file mode 100644
index 0000000000..101bb99f52
--- /dev/null
+++ b/src/mainboard/aoostar/wtr_r1/devicetree.cb
@@ -0,0 +1,212 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/alderlake
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	register "sagv" = "SaGv_Enabled"
+
+	register "dptf_enable" = "1"
+
+	register "s0ix_enable" = "1"
+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	# Configure external V1P05/Vnn/VnnSx Rails
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
+		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
+		.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
+		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
+		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
+		.v1p05_voltage_mv = 1050,
+		.vnn_voltage_mv = 780,
+		.vnn_sx_voltage_mv = 1050,
+		.v1p05_icc_max_ma = 500,
+		.vnn_icc_max_ma = 500,
+	}"
+
+	device domain 0 on
+		device ref igpu on
+			register "ddi_portA_config" = "1"
+			register "ddi_portB_config" = "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			}"
+		end
+		device ref dtt on end
+		device ref crashlog off end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)"	# USB3/2 Type A upper
+		end
+		device ref xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_TYPE_C(OC0),		/* Type-C */
+				[1] = USB2_PORT_MID(OC_SKIP),		/* microSD card reader */
+				[2] = USB2_PORT_MID(OC3),		/* USB2 Type A upper */
+				[3] = USB2_PORT_MID(OC3),		/* USB2 Type A lower */
+				[4] = USB2_PORT_MID(OC3),		/* USB3/2 Type A upper */
+				[5] = USB2_PORT_MID(OC3),		/* USB3/2 Type A lower */
+				[7] = USB2_PORT_MID(OC_SKIP),		/* M.2 WLAN */
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),		/* Type-C */
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* microSD card reader */
+				[5] = USB3_PORT_DEFAULT(OC3),		/* USB3/2 Type A lower */
+				[6] = USB3_PORT_DEFAULT(OC3),		/* USB3/2 Type A upper */
+			}"
+		end
+		device ref cnvi_wifi on
+			register "cnvi_bt_core" = "true"
+			register "cnvi_bt_audio_offload" = "true"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+		end
+		device ref i2c1 on
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+		end
+		device ref i2c2 on
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+		end
+		device ref i2c3 on
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
+		end
+		device ref sata on
+			register "sata_salp_support" = "1"
+			register "sata_ports_enable" = "{
+				[0] = 1,
+				[1] = 1,
+			}"
+			register "sata_ports_dev_slp" = "{
+				[0] = 1,
+				[1] = 1,
+			}"
+		end
+		device ref i2c5 on
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
+		end
+		device ref pcie_rp3 on
+			register "pch_pcie_rp[PCH_RP(3)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_CLK_REQ_DETECT,
+			}"
+			smbios_slot_desc	"SlotTypeM2Socket3" "SlotLengthOther"
+						"M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth2X"
+		end
+		device ref pcie_rp7 on	# LAN1
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_CLK_REQ_DETECT,
+			}"
+		end
+		device ref pcie_rp9 on	# LAN2
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_CLK_REQ_DETECT,
+			}"
+		end
+		device ref pcie_rp10 on
+			register "pch_pcie_rp[PCH_RP(10)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_CLK_REQ_DETECT,
+			}"
+			smbios_slot_desc	"SlotTypeM2Socket1_SD" "SlotLengthOther"
+						"M.2/E 2230 (M2_WIFI1)" "SlotDataBusWidth1X"
+		end
+		device ref pch_espi on
+			# Needed for ITE SuperIO
+			register "gen1_dec" = "0x00fc0201"
+			register "gen2_dec" = "0x007c0a01"
+			register "gen3_dec" = "0x000c03e1"
+			register "gen4_dec" = "0x001c02e1"
+			chip superio/ite/it8613e
+				register "TMPIN1.mode"   = "THERMAL_RESISTOR"
+				register "ec.vin_mask"   = "VIN_ALL"
+				# CPU_FAN1
+				register "FAN2.mode" = "FAN_SMART_AUTOMATIC"
+				register "FAN2.smart.tmpin"     = " 1"
+				register "FAN2.smart.tmp_off"   = "32" # Vendor default: 30
+				register "FAN2.smart.tmp_start" = "35"
+				register "FAN2.smart.tmp_full"  = "96"
+				register "FAN2.smart.tmp_delta" = " 1" # Vendor default: 2
+				register "FAN2.smart.pwm_start" = "30" # Vendor default: 40
+				register "FAN2.smart.slope"     = " 1"
+				# SYSFANCN1
+				register "FAN3.mode" = "FAN_SMART_SOFTWARE"
+				register "FAN3.smart.pwm_start" = "80"
+				# SYS_FAN1
+				register "FAN4.mode" = "FAN_SMART_SOFTWARE"
+				register "FAN4.smart.pwm_start" = "127"
+
+				device pnp 2e.0 off end # Floppy
+				device pnp 2e.1 off end # COM 1
+				device pnp 2e.4 on	# Environment Controller
+					io 0x60 = 0xa30
+					io 0x62 = 0xa20
+					irq 0x70 = 0x00
+				end
+				device pnp 2e.5 off end # Keyboard
+				device pnp 2e.6 off end # Mouse
+				device pnp 2e.7 on	# GPIO
+					io 0x60 = 0x000
+					io 0x62 = 0xa00
+					irq 0x70 = 0x00
+					irq 0x71 = 0x01
+				end
+				device pnp 2e.a off end # CIR
+			end
+		end
+		device ref uart0 on
+			register "serial_io_uart_mode" = "{
+				[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+			}"
+		end
+		device ref gspi0 on
+			register "serial_io_gspi_mode" = "{
+				[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+			}"
+		end
+		device ref ish on end
+		device ref hda on
+			register "pch_hda_dsp_enable" = "1"
+			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+			register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_codec_enable" = "1"
+		end
+		device ref smbus on end
+	end
+end
diff --git a/src/mainboard/aoostar/wtr_r1/dsdt.asl b/src/mainboard/aoostar/wtr_r1/dsdt.asl
new file mode 100644
index 0000000000..58c147e56c
--- /dev/null
+++ b/src/mainboard/aoostar/wtr_r1/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <gpio.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/alderlake/acpi/southbridge.asl>
+		#include <soc/intel/alderlake/acpi/tcss.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/aoostar/wtr_r1/gpio.h b/src/mainboard/aoostar/wtr_r1/gpio.h
new file mode 100644
index 0000000000..067b9cebb3
--- /dev/null
+++ b/src/mainboard/aoostar/wtr_r1/gpio.h
@@ -0,0 +1,330 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CFG_GPIO_H
+#define CFG_GPIO_H
+
+#include <gpio.h>
+
+#ifndef PAD_CFG_GPIO_BIDIRECT
+#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own)		\
+	_PAD_CFG_STRUCT(pad,						\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) |	\
+		PAD_BUF(NO_DISABLE) | val,				\
+		PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
+#endif
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),	/* CORE_VID0 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),	/* CORE_VID1 */
+	PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1),	/* VRALERT# */
+	PAD_NC(GPP_B3, NONE),
+	PAD_NC(GPP_B4, NONE),
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	PAD_NC(GPP_B9, NONE),
+	PAD_NC(GPP_B10, NONE),
+	PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1),	/* PMCALERT# */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),	/* SLP_S0# */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),	/* PLTRST# */
+	PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1),	/* SPKR */
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_GPO(GPP_B18, 0, DEEP),
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_NC(GPP_B22, NONE),
+	PAD_CFG_GPO(GPP_B23, 0, DEEP),
+	PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1),	/* GSPI0_CLK_LOOPBK */
+	PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1),	/* GSPI1_CLK_LOOPBK */
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T0, NONE),
+	PAD_NC(GPP_T1, NONE),
+	PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2),	/* FUSA_DIAGTEST_EN */
+	PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2),	/* FUSA_DIAGTEST_MODE */
+	PAD_NC(GPP_T4, NONE),
+	PAD_NC(GPP_T5, NONE),
+	PAD_NC(GPP_T6, NONE),
+	PAD_NC(GPP_T7, NONE),
+	PAD_NC(GPP_T8, NONE),
+	PAD_NC(GPP_T9, NONE),
+	PAD_NC(GPP_T10, NONE),
+	PAD_NC(GPP_T11, NONE),
+	PAD_NC(GPP_T12, NONE),
+	PAD_NC(GPP_T13, NONE),
+	PAD_NC(GPP_T14, NONE),
+	PAD_NC(GPP_T15, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),	/* ESPI_IO0 */
+	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),	/* ESPI_IO1 */
+	PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),	/* ESPI_IO2 */
+	PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),	/* ESPI_IO3 */
+	PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),	/* ESPI_CS0# */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),	/* ESPI_ALERT0# */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),	/* ESPI_ALERT1# */
+	PAD_NC(GPP_A7, NONE),
+	PAD_NC(GPP_A8, NONE),
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),	/* ESPI_CLK */
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),	/* ESPI_RESET# */
+	PAD_NC(GPP_A11, NONE),
+	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),	/* SATAXPCIE1 */
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),	/* USB_OC1# */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),	/* USB_OC2# */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),	/* USB_OC3# */
+	PAD_NC(GPP_A17, NONE),
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),	/* DDSP_HPDB */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),	/* DDSP_HPD1 */
+	PAD_NC(GPP_A20, NONE),
+	PAD_CFG_GPO(GPP_A21, 1, PLTRST),
+	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),	/* DDPC_CTRLDATA */
+	PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1),	/* ESPI_CS1# */
+	PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1),	/* GPP_ESPI_CLK_LOOPBK */
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_I ------- */
+	PAD_NC(GPP_I0, NONE),
+	PAD_NC(GPP_I1, NONE),
+	PAD_NC(GPP_I2, NONE),
+	PAD_NC(GPP_I3, NONE),
+	PAD_NC(GPP_I4, NONE),
+	PAD_NC(GPP_I5, NONE),
+	PAD_NC(GPP_I6, NONE),
+	PAD_NC(GPP_I7, NONE),
+	PAD_NC(GPP_I8, NONE),
+	PAD_NC(GPP_I9, NONE),
+	PAD_NC(GPP_I10, NONE),
+	PAD_NC(GPP_I11, NONE),
+	PAD_NC(GPP_I12, NONE),
+	PAD_NC(GPP_I13, NONE),
+	PAD_NC(GPP_I14, NONE),
+	PAD_NC(GPP_I15, NONE),
+	PAD_NC(GPP_I16, NONE),
+	PAD_NC(GPP_I17, NONE),
+	PAD_NC(GPP_I18, NONE),
+	PAD_NC(GPP_I19, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_GPO(GPP_H0, 0, DEEP),
+	PAD_CFG_GPO(GPP_H1, 0, DEEP),
+	PAD_CFG_GPO(GPP_H2, 0, DEEP),
+	PAD_CFG_GPO(GPP_H3, 1, PLTRST),
+	PAD_NC(GPP_H4, NONE),
+	PAD_NC(GPP_H5, NONE),
+	PAD_NC(GPP_H6, NONE),
+	PAD_NC(GPP_H7, NONE),
+	PAD_NC(GPP_H8, NONE),
+	PAD_NC(GPP_H9, NONE),
+	PAD_NC(GPP_H10, NONE),
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),	/* n/a */
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H13, NONE),
+	PAD_NC(GPP_H14, NONE),
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),	/* DDPB_CTRLCLK */
+	PAD_NC(GPP_H16, NONE),
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),	/* DDPB_CTRLDATA */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),	/* PROC_C10_GATE# */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),	/* SRCCLKREQ4# */
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_NC(GPP_H23, NONE),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),	/* SRCCLKREQ0# */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),	/* SRCCLKREQ1# */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),	/* SRCCLKREQ2# */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),	/* SRCCLKREQ3# */
+	PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF5),	/* BSSB_LS2_RX */
+	PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF5),	/* BSSB_LS2_TX */
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF5),	/* BSSB_LS3_RX */
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF5),	/* BSSB_LS3_TX */
+	PAD_NC(GPP_D13, NONE),
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),	/* UART1_RXD */
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),	/* UART1_TXD */
+	PAD_NC(GPP_D19, NONE),
+	PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1),	/* GPP_GSPI2_CLK_LOOPBK */
+
+	/* ------- GPIO Group vGPIO ------- */
+	PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI),
+	PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1),	/* GPP_VGPIO_6 */
+	PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1),	/* GPP_VGPIO_7 */
+	PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1),	/* GPP_VGPIO_8 */
+	PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1),	/* GPP_VGPIO_9 */
+	PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1),	/* GPP_VGPIO_10 */
+	PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1),	/* GPP_VGPIO_11 */
+	PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1),	/* GPP_VGPIO_12 */
+	PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1),	/* GPP_VGPIO_13 */
+	PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1),	/* GPP_VGPIO_18 */
+	PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1),	/* GPP_VGPIO_19 */
+	PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1),	/* GPP_VGPIO_20 */
+	PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1),	/* GPP_VGPIO_21 */
+	PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1),	/* GPP_VGPIO_22 */
+	PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1),	/* GPP_VGPIO_23 */
+	PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1),	/* GPP_VGPIO_24 */
+	PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1),	/* GPP_VGPIO_25 */
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1),	/* GPP_VGPIO_30 */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1),	/* GPP_VGPIO_31 */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1),	/* GPP_VGPIO_32 */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1),	/* GPP_VGPIO_33 */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),	/* GPP_VGPIO_34 */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),	/* GPP_VGPIO_35 */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),	/* GPP_VGPIO_36 */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),	/* GPP_VGPIO_37 */
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* ------- GPIO Group GPP_GPD ------- */
+	PAD_CFG_NF(GPD0, NONE, PWROK, NF1),	/* BATLOW# */
+	PAD_CFG_NF(GPD1, NONE, PWROK, NF1),	/* ACPRESENT */
+	PAD_CFG_GPO(GPD2, 1, PLTRST),
+	PAD_CFG_NF(GPD3, NONE, PWROK, NF1),	/* PWRBTN# */
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),	/* SLP_S3# */
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),	/* SLP_S4# */
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),	/* SLP_A# */
+	PAD_CFG_GPO(GPD7, 0, PWROK),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),	/* SUSCLK */
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),	/* SLP_WLAN# */
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),	/* SLP_S5# */
+	PAD_CFG_GPO(GPD11, 0, PWROK),
+	PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1),	/* GPD_INPUT3VSEL */
+	PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1),	/* GPD_SLP_LANB */
+	PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1),	/* GPD_SLP_SUSB */
+	PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1),	/* GPD_WAKEB */
+	PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1),	/* GPD_DRAM_RESETB */
+
+	/* ------- GPIO Community 4 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),	/* SMBCLK */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),	/* SMBDATA */
+	PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1),	/* SMBALERT# */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),	/* SML0CLK */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),	/* SML0DATA */
+	PAD_CFG_TERM_GPO(GPP_C5, 1, DN_20K, PLTRST),
+	PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1),	/* SML1CLK */
+	PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1),	/* SML1DATA */
+	PAD_NC(GPP_C8, NONE),
+	PAD_NC(GPP_C9, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_NC(GPP_C16, NONE),
+	PAD_NC(GPP_C17, NONE),
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),	/* CNV_BRI_DT */
+	PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),	/* CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),	/* CNV_RGI_DT */
+	PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),	/* CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),	/* CNV_RF_RESET# */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),	/* n/a */
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),	/* CNV_PA_BLANKING */
+	PAD_CFG_GPO(GPP_F7, 0, DEEP),
+	PAD_NC(GPP_F8, NONE),
+	PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),	/* BOOTMPC */
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F17, NONE),
+	PAD_NC(GPP_F18, NONE),
+	PAD_NC(GPP_F19, NONE),
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),	/* Reserved */
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),	/* Reserved */
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+	PAD_NC(GPP_F_CLK_LOOPBK, NONE),
+
+	/* ------- GPIO Group GPP_HVCMOS ------- */
+	PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1),	/* n/a */
+	PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1),	/* n/a */
+	PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1),	/* n/a */
+	PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1),	/* n/a */
+	PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1),	/* n/a */
+	PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1),	/* n/a */
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1),	/* SATAXPCIE0 */
+	PAD_NC(GPP_E1, NONE),
+	PAD_NC(GPP_E2, NONE),
+	PAD_NC(GPP_E3, NONE),
+	PAD_NC(GPP_E4, NONE),
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_TERM_GPO(GPP_E6, 1, DN_20K, PLTRST),
+	PAD_NC(GPP_E7, NONE),
+	PAD_CFG_GPO(GPP_E8, 0, PLTRST),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),	/* USB_OC0# */
+	PAD_NC(GPP_E10, NONE),
+	PAD_NC(GPP_E11, NONE),
+	PAD_NC(GPP_E12, NONE),
+	PAD_NC(GPP_E13, NONE),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),	/* DDSP_HPDA */
+	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2),	/* Reserved */
+	PAD_CFG_GPO(GPP_E16, 0, PLTRST),
+	PAD_NC(GPP_E17, NONE),
+	PAD_NC(GPP_E18, NATIVE),
+	PAD_NC(GPP_E19, NATIVE),
+	PAD_CFG_NF(GPP_E20, NATIVE, DEEP, NF5),	/* BSSB_LS1_RX */
+	PAD_CFG_NF(GPP_E21, NATIVE, DEEP, NF5),	/* BSSB_LS1_TX */
+	PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1),	/* DDPA_CTRLCLK */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),	/* DDPA_CTRLDATA */
+	PAD_NC(GPP_E_CLK_LOOPBK, NONE),
+
+	/* ------- GPIO Community 5 ------- */
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),	/* HDA_BCLK */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1),	/* HDA_SYNC */
+	PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1),	/* HDA_SDO */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1),	/* HDA_SDI0 */
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),	/* HDA_RST# */
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+};
+
+#endif /* CFG_GPIO_H */
diff --git a/src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c b/src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c
new file mode 100644
index 0000000000..1477bc038a
--- /dev/null
+++ b/src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <soc/meminit.h>
+
+#include "gpio.h"
+
+static const struct mb_cfg ddr4_mem_config = {
+	.type = MEM_TYPE_DDR4,
+	/* According to DOC #573387 rcomp values no longer have to be provided */
+	/* DDR DIMM configuration does not need to set DQ/DQS maps */
+
+	.ect = true, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	},
+};
+
+static const struct mem_spd dimm_module_spd_info = {
+	.topo = MEM_TOPO_DIMM_MODULE,
+	.smbus[0] = { .addr_dimm[0] = 0x50, },
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	/*
+	 * Alder Lake common meminit block driver considers bus width to be 128-bit and
+	 * populates the meminit data accordingly. Alder Lake-N has single memory controller
+	 * with 64-bit bus width. By setting half_populated to true, only the bottom half is
+	 * populated.
+	 * TODO: Implement __weak variant_is_half_populated(void) function.
+	 */
+	const bool half_populated = true;
+
+	memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, half_populated);
+
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}