mb/*/*: Remove AMD family14 boards

These boards use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I3495d140a244bbbf63e846fcd963d69907e09719
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

88 files changed, 0 insertions, 7838 deletions

diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
deleted file mode 100644
index 72bd046b5b..0000000000
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <amdlib.h>
-#include <amdblocks/acpimmio.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <SB800.h>
-#include <southbridge/amd/cimx/sb800/gpio_oem.h>
-
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GNB_PCIE_SLOT_RESET,		board_GnbPcieSlotReset },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
-	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/*  Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS      Status;
-	MEM_DATA_STRUCT   *MemData;
-	UINT32            GpioMmioAddr;
-	UINT8             Data8;
-	UINT8             TempData8;
-
-	MemData = ConfigPtr;
-
-	Status  = AGESA_SUCCESS;
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-
-	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	Data8 &= ~BIT5;
-	TempData8  = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
-
-	Data8 |= BIT2 | BIT3;
-	Data8 &= ~BIT4;
-	TempData8  = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
-
-	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	Data8 &= ~BIT5;
-	TempData8  = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
-
-	Data8 |= BIT2 | BIT3;
-	Data8 &= ~BIT4;
-	TempData8  = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
-
-	switch (MemData->ParameterListPtr->DDR3Voltage) {
-	case VOLT1_35:
-		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_25:
-		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_5:
-	default:
-		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-	}
-	return Status;
-}
-
-/* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS Status;
-	PCIe_SLOT_RESET_INFO  *ResetInfo;
-
-	UINT32  GpioMmioAddr;
-	UINT8   Data8;
-
-	ResetInfo = ConfigPtr;
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-	Status = AGESA_UNSUPPORTED;
-	switch (ResetInfo->ResetId) {
-	case 4:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
-			Data8 &= ~(UINT8)BIT6;
-			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
-			Data8 |= BIT6;
-			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	case 6:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
-			Data8 &= ~(UINT8)BIT6;
-			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
-			Data8 |= BIT6;
-			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	case 7:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
-			Data8 &= ~(UINT8)BIT6;
-			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
-			Data8 |= BIT6;
-			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	}
-	return Status;
-}
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
deleted file mode 100644
index 3706b3335d..0000000000
--- a/src/mainboard/amd/inagua/Kconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_AMD_INAGUA
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY14
-	select NORTHBRIDGE_AMD_AGESA_FAMILY14
-	select SOUTHBRIDGE_AMD_CIMX_SB800
-	select SUPERIO_SMSC_KBC1100
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_2048
-	select GFXUMA
-
-config MAINBOARD_DIR
-	default "amd/inagua"
-
-config MAINBOARD_PART_NUMBER
-	default "Inagua"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 2
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS_ID
-	string "VGA device PCI IDs"
-	depends on VGA_BIOS
-	default "1002,9802"
-
-config SB800_AHCI_ROM
-	bool
-	default n
-
-endif # BOARD_AMD_INAGUA
diff --git a/src/mainboard/amd/inagua/Kconfig.name b/src/mainboard/amd/inagua/Kconfig.name
deleted file mode 100644
index 668b22a7d7..0000000000
--- a/src/mainboard/amd/inagua/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_AMD_INAGUA
-	bool "Inagua"
diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc
deleted file mode 100644
index 9655909056..0000000000
--- a/src/mainboard/amd/inagua/Makefile.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-ifeq ($(CONFIG_AHCI_BIOS),y)
-stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
-cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
-pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
-pci$(stripped_ahcibios_id).rom-type := optionrom
-endif
-
-bootblock-y += bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c
deleted file mode 100644
index 0338115439..0000000000
--- a/src/mainboard/amd/inagua/OemCustomize.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <PlatformMemoryConfiguration.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 4)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 6)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 7)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeLvds, Aux1, Hdp1)
-	},
-	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux2, Hdp2)
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
-	PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
diff --git a/src/mainboard/amd/inagua/OptionsIds.h b/src/mainboard/amd/inagua/OptionsIds.h
deleted file mode 100644
index fdd5de0cd1..0000000000
--- a/src/mainboard/amd/inagua/OptionsIds.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-
-#endif
diff --git a/src/mainboard/amd/inagua/acpi/gpe.asl b/src/mainboard/amd/inagua/acpi/gpe.asl
deleted file mode 100644
index 44e7b68eac..0000000000
--- a/src/mainboard/amd/inagua/acpi/gpe.asl
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/amd/inagua/acpi/ide.asl b/src/mainboard/amd/inagua/acpi/ide.asl
deleted file mode 100644
index e3a1bec04e..0000000000
--- a/src/mainboard/amd/inagua/acpi/ide.asl
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Local0 = Arg0 & 0x0F	/* Recovery Width */
-	Local0++
-	Local1 = Arg0 >> 4	/* Command Width */
-	Local1++
-	Return(30 * (Local0 + Local1))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0, Serialized)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If (PPCR & 0x01) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		BFFG |= 0x1A
-
-		PSD0 = GTTM (PPTM) /* save total time of primary PIO master timing  to PIO spd0 */
-		PSD1 = GTTM (PPTS) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If (PDCR & 0x01) {	/* It's under UDMA mode */
-			BFFG |= 0x01
-			DSD0 = DerefOf(UDTT [PDMM])
-		}
-		Else {
-			DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If (PDCR & 0x02) {	/* It's under UDMA mode */
-			BFFG |= 0x04
-			DSD1 = DerefOf(UDTT [PDSM])
-		}
-		Else {
-			DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, Serialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0)
-		PPMM = Local0 % 5 /* Primary PIO master Mode */
-		Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0)
-		PPSM = Local1 % 5 /* Primary PIO slave Mode */
-
-		PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */
-		PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */
-
-		If (BFFG & 0x01) {	/* Drive 0 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0)
-			PDMM = Local0 % 7
-			PDCR |= 0x01
-		}
-		Else {
-			If (DSD0 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0)
-				PMTM = DerefOf(MDRT [Local0])
-			}
-		}
-
-		If (BFFG & 0x04) {	/* Drive 1 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0)
-			PDSM = Local0 % 7
-			PDCR |= 0x02
-		}
-		Else {
-			If (DSD1 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0)
-				PMTS = DerefOf(MDRT [Local0])
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xA0
-			CMDB = 0xA0
-			CMDC = 0xA0
-
-			POMD = PPMM | 0x08
-
-			If (PDCR & 0x01) {
-				DMMD = PDMM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xB0
-			CMDB = 0xB0
-			CMDC = 0xB0
-
-			POMD = PPSM | 0x08
-
-			If (PDCR & 0x02) {
-				DMMD = PDSM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}
diff --git a/src/mainboard/amd/inagua/acpi/routing.asl b/src/mainboard/amd/inagua/acpi/routing.asl
deleted file mode 100644
index 8f8ea45e9e..0000000000
--- a/src/mainboard/amd/inagua/acpi/routing.asl
+++ /dev/null
@@ -1,382 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		Package(){0x0009FFFF, 0, INTB, 0 },
-		Package(){0x0009FFFF, 1, INTC, 0 },
-		Package(){0x0009FFFF, 2, INTD, 0 },
-		Package(){0x0009FFFF, 3, INTA, 0 },
-
-		Package(){0x000AFFFF, 0, INTC, 0 },
-		Package(){0x000AFFFF, 1, INTD, 0 },
-		Package(){0x000AFFFF, 2, INTA, 0 },
-		Package(){0x000AFFFF, 3, INTB, 0 },
-
-		Package(){0x000BFFFF, 0, INTD, 0 },
-		Package(){0x000BFFFF, 1, INTA, 0 },
-		Package(){0x000BFFFF, 2, INTB, 0 },
-		Package(){0x000BFFFF, 3, INTC, 0 },
-
-		Package(){0x000CFFFF, 0, INTA, 0 },
-		Package(){0x000CFFFF, 1, INTB, 0 },
-		Package(){0x000CFFFF, 2, INTC, 0 },
-		Package(){0x000CFFFF, 3, INTD, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 9 - PCIe Bridge for network card */
-		Package(){0x0009FFFF, 0, 0, 17 },
-		Package(){0x0009FFFF, 1, 0, 16 },
-		Package(){0x0009FFFF, 2, 0, 17 },
-		Package(){0x0009FFFF, 3, 0, 18 },
-		/* Bus 0, Dev A - PCIe Bridge for network card */
-		Package(){0x000AFFFF, 0, 0, 18 },
-		Package(){0x000AFFFF, 1, 0, 16 },
-		Package(){0x000AFFFF, 2, 0, 17 },
-		Package(){0x000AFFFF, 3, 0, 18 },
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-		/* Package(){0x0012FFFF, 2, 0, 18 }, */
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-		/* Package(){0x0013FFFF, 2, 0, 16 }, */
-
-		/* Package(){0x00140000, 0, 0, 16 }, */
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: pcie */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-		Package(){0x0007FFFF, 0, 0, 0x16 },
-		Package(){0x0007FFFF, 1, 0, 0x17 },
-		Package(){0x0007FFFF, 2, 0, 0x14 },
-		Package(){0x0007FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/amd/inagua/acpi/sata.asl b/src/mainboard/amd/inagua/acpi/sata.asl
deleted file mode 100644
index e924b571cd..0000000000
--- a/src/mainboard/amd/inagua/acpi/sata.asl
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P0IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P1IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P2IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P3IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (\_SB.P0IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			 \_SB.P0PR = 1
-		}
-
-		if (\_SB.P1PR) {
-			if (\_SB.P1IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P1PR = 1
-		}
-
-		if (\_SB.P2PR) {
-			if (\_SB.P2IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P2PR = 1
-		}
-
-		if (\_SB.P3PR) {
-			if (\_SB.P3IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P3PR = 1
-		}
-	}
-}
diff --git a/src/mainboard/amd/inagua/acpi/sleep.asl b/src/mainboard/amd/inagua/acpi/sleep.asl
deleted file mode 100644
index 3b6fd02055..0000000000
--- a/src/mainboard/amd/inagua/acpi/sleep.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Don't allow PCIRST# to reset USB */
-	if (Arg0 == 3){
-		URRE = 0
-	}
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	HPDE = 1
-
-	/* Restore PCIRST# so it resets USB */
-	if (Arg0 == 3){
-		URRE = 1
-	}
-
-	/* Arbitrarily clear PciExpWakeStatus */
-	Local1 = PWST
-	PWST = Local1
-
-	/* if (DeRefOf(WKST [0])) {
-	*	WKST [1] = 0
-	* } else {
-	*	WKST [1] = Arg0
-	* }
-	*/
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/amd/inagua/acpi/superio.asl b/src/mainboard/amd/inagua/acpi/superio.asl
deleted file mode 100644
index 16990d45f4..0000000000
--- a/src/mainboard/amd/inagua/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/amd/inagua/acpi/usb_oc.asl b/src/mainboard/amd/inagua/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/amd/inagua/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
-	Sleep(20)
-	CMTI = 0x13
-	GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if (GPB0 == PLC0) {
-				PLC0 = ~PLC0
-				\_SB.PT0D = PLC0
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (GPB1 == PLC1) {
-				PLC1 = ~PLC1
-				\_SB.PT1D = PLC1
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (GPB2 == PLC2) {
-				PLC2 = ~PLC2
-				\_SB.PT2D = PLC2
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (GPB3 == PLC3) {
-				PLC3 = ~PLC3
-				\_SB.PT3D = PLC3
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (GPB4 == PLC4) {
-				PLC4 = ~PLC4
-				\_SB.PT4D = PLC4
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (GPB5 == PLC5) {
-				PLC5 = ~PLC5
-				\_SB.PT5D = PLC5
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (GPB6 == PLC6) {
-				PLC6 = ~PLC6
-				\_SB.PT6D = PLC6
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (GPB7 == PLC7) {
-				PLC7 = ~PLC7
-				\_SB.PT7D = PLC7
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (G8IS == PLC8) {
-				PLC8 = ~PLC8
-				\_SB.PT8D = PLC8
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (G9IS == 0) {
-			\_SB.PT9D = 1
-			}
-		}
-	}
-}
diff --git a/src/mainboard/amd/inagua/board_info.txt b/src/mainboard/amd/inagua/board_info.txt
deleted file mode 100644
index b351b8e696..0000000000
--- a/src/mainboard/amd/inagua/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: eval
diff --git a/src/mainboard/amd/inagua/bootblock.c b/src/mainboard/amd/inagua/bootblock.c
deleted file mode 100644
index a13136c105..0000000000
--- a/src/mainboard/amd/inagua/bootblock.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <superio/smsc/kbc1100/kbc1100.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
-void bootblock_mainboard_early_init(void)
-{
-	kbc1100_early_init(0x2e);
-	kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
deleted file mode 100644
index 73216349ce..0000000000
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_14_SUPPORT		TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
-
-/* Agesa optional capabilities selection */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
-#define BLDOPT_REMOVE_WHEA			FALSE
-
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
-
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-#define BLDCFG_S3_LATE_RESTORE			FALSE
-#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
-
-/* Agesa configuration values selection */
-#include <AGESA.h>
-
-/* Include the files that instantiate the configuration definitions */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/* Instantiate all solution relevant data */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/amd/inagua/cmos.layout b/src/mainboard/amd/inagua/cmos.layout
deleted file mode 100644
index a11e1dd0e6..0000000000
--- a/src/mainboard/amd/inagua/cmos.layout
+++ /dev/null
@@ -1,35 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-400	1	e	1	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
deleted file mode 100644
index d5a4e45415..0000000000
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ /dev/null
@@ -1,74 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family14
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1510 inherit
-		chip northbridge/amd/agesa/family14
-			device pci 0.0 on end # Root Complex
-			device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
-			device pci 1.1 on end # Internal HDMI Audio
-			device pci 4.0 on  end # PCIE P2P bridge MXM lane 0
-			device pci 5.0 off end # PCIE P2P bridge MXM lane 1
-			device pci 6.0 on end # PCIE P2P bridge  LAN
-			device pci 7.0 on end # PCIE P2P bridge  MINIPCIE SLOT1
-			device pci 8.0 off end # NB/SB Link P2P bridge
-		end # agesa northbridge
-
-		chip southbridge/amd/cimx/sb800
-			device pci 11.0 on end # SATA
-			device pci 12.0 on end # OHCI USB 0-4
-			device pci 12.2 on end # EHCI USB 0-4
-			device pci 13.0 on end # OHCI USB 5-9
-			device pci 13.2 on end # EHCI USB 5-9
-			device pci 14.0 on end # SM
-			device pci 14.1 on end # IDE    0x439c
-			device pci 14.2 on end # HDA    0x4383
-			device pci 14.3 on # LPC	0x439d
-				chip superio/smsc/kbc1100
-					device pnp 2e.7 on #  Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-					end
-				end # kbc1100
-			end #LPC
-			device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-			device pci 14.5 on end # OHCI FS/LS USB
-			device pci 14.6 on end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
-			device pci 15.0 on end # PCIe PortA  Express Card
-			device pci 15.1 on end # PCIe PortB  NEC USB3.0
-			device pci 15.2 on end # PCIe PortC  MINIPCIE SLOT2
-			device pci 15.3 on end # PCIe PortD  PCIE X1 SLOT
-			device pci 16.0 on end # OHCI USB 10-13
-			device pci 16.2 on end # EHCI USB 10-13
-			register "gpp_configuration" = "4" #1:1:1:1
-			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-		end	#southbridge/amd/cimx/sb800
-
-		chip northbridge/amd/agesa/family14
-
-			# These seem unnecessary
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-			device pci 18.6 on end
-			device pci 18.7 on end
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-
-		end # agesa northbridge
-
-	end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl
deleted file mode 100644
index 834a2cfbf9..0000000000
--- a/src/mainboard/amd/inagua/dsdt.asl
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	#include <cpu/amd/agesa/family14/acpi/cpu.asl>
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		Device(PCI0) {
-
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
-
-			/* Primary (and only) IDE channel */
-			Device(IDEC) {
-				Name(_ADR, 0x00140001)
-				#include "acpi/ide.asl"
-			} /* end IDEC */
-
-		}
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	#include "acpi/gpe.asl"
-	#include "acpi/usb_oc.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c
deleted file mode 100644
index e5d576a349..0000000000
--- a/src/mainboard/amd/inagua/irq_tables.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *)(addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* PCI bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum)
-		pirq->checksum = sum;
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
deleted file mode 100644
index d364649207..0000000000
--- a/src/mainboard/amd/inagua/mainboard.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/acpimmio_legacy_gpio100.h>
-#include <device/device.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static const u8 mainboard_intr_data[] = {
-	[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,  /* INTA# - INTH# */
-	[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,  /* Misc-nil, 0, 1, 2,  INT from Serial irq */
-	[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00,
-	[0x18] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
-	[0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	[0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
-	[0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	[0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	[0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	[0x50] = 0x10, 0x11, 0x12, 0x13
-};
-
-static void init_gpios(void)
-{
-	/**
-	 * GPIO32 Pcie Device DeAssert for APU
-	 * GPIO25 Pcie LAN,       APU GPP2
-	 * GPIO02 MINIPCIE SLOT1, APU GPP3
-	 * GPIO50 Pcie Device DeAssert for Hudson Southbridge
-	 * GPIO05 Express Card,     SB  GPP0
-	 * GPIO26 NEC USB3.0GPPUSB, SB  GPP1
-	 * GPIO00 MINIPCIE SLOT2,   SB  GPP2
-	 * GPIO05 Pcie X1 Slot,     SB  GPP3
-	 */
-
-	/* Multi-function pins switch to GPIO0-35, these pins are shared with
-	 * PCI pins, make sure Hudson PCI device is disabled.
-	 */
-	pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1);
-
-	/* select IOMux to function1/2, corresponds to GPIO */
-	iomux_write8(0x32, (iomux_read8(0x32) & 0xfc) | 1);
-	iomux_write8(0x50, (iomux_read8(0x50) & 0xfc) | 2);
-
-	/* output low */
-	gpio_100_write8(0x20, 0x48);
-	gpio_100_write8(0x32, 0x48);
-}
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	intr_data_ptr = mainboard_intr_data;
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-
-	/* Inagua mainboard specific setting */
-	init_gpios();
-
-	/*
-	 * Initialize ASF registers to an arbitrary address because someone
-	 * long ago set things up this way inside the SPD read code.  The
-	 * SPD read code has been made generic and moved out of the board
-	 * directory, so the ASF init is being done here.
-	 */
-	pm_write8(0x29, 0x80);
-	pm_write8(0x28, 0x61);
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h
deleted file mode 100644
index 85a60e251b..0000000000
--- a/src/mainboard/amd/inagua/platform_cfg.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-/**
- * @def BIOS_SIZE
- *      BIOS_SIZE_{1,2,4,8,16}M
- *
- * In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM			0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER			1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
- *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
- *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
- *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
- *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
- *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
- *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
- */
-#define USB_CONFIG		0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL			0x1F
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_MODE			CONFIG_SB800_SATA_MODE
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE			0
-#define IDE_NATIVE_MODE			1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_IDE_MODE			IDE_LEGACY_MODE
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK		0x00
-#define INTERNAL_CLOCK		0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED	1
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO			0
-#define AZALIA_DISABLE			1
-#define AZALIA_ENABLE			2
-
-/**
- * @brief INCHIP HDA controller
- */
-#define AZALIA_CONTROLLER		AZALIA_AUTO
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#define AZALIA_PIN_CONFIG		1
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is defined at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is defined at BIT2 & BIT3
- *  SDIN2 is defined at BIT4 & BIT5
- *  SDIN3 is defined at BIT6 & BIT7
- */
-//#define AZALIA_SDIN_PIN		0xAA
-#define AZALIA_SDIN_PIN			0x2A
-
-/**
- * @def GPP_CONTROLLER
- */
-#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#define GPP_CFGMODE			GPP_CFGMODE_X1111
-
-/**
- * @def NB_SB_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define NB_SB_GEN2			TRUE
-
-/**
- * @def SB_GPP_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define SB_GPP_GEN2			TRUE
-
-/**
- * @def SB_GPP_UNHIDE_PORTS
- *    TRUE   - ports visible always, even port empty
- *    FALSE  - ports invisible if port empty
- */
-#define SB_GPP_UNHIDE_PORTS		FALSE
-
-/**
- * @def   GEC_CONFIG
- *    0  - Enable
- *    1  - Disable
- */
-#define GEC_CONFIG			0
-
-#endif
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
deleted file mode 100644
index fb978b8287..0000000000
--- a/src/mainboard/amd/persimmon/BiosCallOuts.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <amdlib.h>
-#include <amdblocks/acpimmio.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <SB800.h>
-
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GNB_PCIE_SLOT_RESET,		board_GnbPcieSlotReset },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
-	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/*	Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	// Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
-	// Make sure the right speed settings are selected.
-	((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
-	return AGESA_SUCCESS;
-}
-
-/* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS Status;
-	PCIe_SLOT_RESET_INFO	*ResetInfo;
-
-	UINT32	GpioMmioAddr;
-	UINT8	 Data8;
-
-	ResetInfo = ConfigPtr;
-	Status = AGESA_UNSUPPORTED;
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-	switch (ResetInfo->ResetId)
-	{
-	case 46:	// GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG50);
-			Data8 &= ~(UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG50, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG50);
-			Data8 |= BIT6;
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG50, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	}
-	return	Status;
-}
diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig
deleted file mode 100644
index 66a05ee3c4..0000000000
--- a/src/mainboard/amd/persimmon/Kconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_AMD_PERSIMMON
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY14
-	select NORTHBRIDGE_AMD_AGESA_FAMILY14
-	select SOUTHBRIDGE_AMD_CIMX_SB800
-	select SUPERIO_FINTEK_F81865F
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_4096
-	select GFXUMA
-
-config MAINBOARD_DIR
-	default "amd/persimmon"
-
-config MAINBOARD_PART_NUMBER
-	default "Persimmon"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 2
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS_ID
-	string
-	default "1002,9802"
-
-config SB800_AHCI_ROM
-	bool
-	default n
-
-endif # BOARD_AMD_PERSIMMON
diff --git a/src/mainboard/amd/persimmon/Kconfig.name b/src/mainboard/amd/persimmon/Kconfig.name
deleted file mode 100644
index ba24b13aa4..0000000000
--- a/src/mainboard/amd/persimmon/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_AMD_PERSIMMON
-	bool "Persimmon"
diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc
deleted file mode 100644
index 9655909056..0000000000
--- a/src/mainboard/amd/persimmon/Makefile.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-ifeq ($(CONFIG_AHCI_BIOS),y)
-stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
-cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
-pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
-pci$(stripped_ahcibios_id).rom-type := optionrom
-endif
-
-bootblock-y += bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c
deleted file mode 100644
index 14fff7da30..0000000000
--- a/src/mainboard/amd/persimmon/OemCustomize.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <PlatformMemoryConfiguration.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 46)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 46)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 46)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeLvds, Aux1, Hdp1)
-	},
-	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *						CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *	Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *	(e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *	is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *	use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
-	PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
diff --git a/src/mainboard/amd/persimmon/OptionsIds.h b/src/mainboard/amd/persimmon/OptionsIds.h
deleted file mode 100644
index fdd5de0cd1..0000000000
--- a/src/mainboard/amd/persimmon/OptionsIds.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-
-#endif
diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl
deleted file mode 100644
index 44e7b68eac..0000000000
--- a/src/mainboard/amd/persimmon/acpi/gpe.asl
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/amd/persimmon/acpi/ide.asl b/src/mainboard/amd/persimmon/acpi/ide.asl
deleted file mode 100644
index e3a1bec04e..0000000000
--- a/src/mainboard/amd/persimmon/acpi/ide.asl
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Local0 = Arg0 & 0x0F	/* Recovery Width */
-	Local0++
-	Local1 = Arg0 >> 4	/* Command Width */
-	Local1++
-	Return(30 * (Local0 + Local1))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0, Serialized)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If (PPCR & 0x01) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		BFFG |= 0x1A
-
-		PSD0 = GTTM (PPTM) /* save total time of primary PIO master timing  to PIO spd0 */
-		PSD1 = GTTM (PPTS) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If (PDCR & 0x01) {	/* It's under UDMA mode */
-			BFFG |= 0x01
-			DSD0 = DerefOf(UDTT [PDMM])
-		}
-		Else {
-			DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If (PDCR & 0x02) {	/* It's under UDMA mode */
-			BFFG |= 0x04
-			DSD1 = DerefOf(UDTT [PDSM])
-		}
-		Else {
-			DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, Serialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0)
-		PPMM = Local0 % 5 /* Primary PIO master Mode */
-		Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0)
-		PPSM = Local1 % 5 /* Primary PIO slave Mode */
-
-		PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */
-		PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */
-
-		If (BFFG & 0x01) {	/* Drive 0 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0)
-			PDMM = Local0 % 7
-			PDCR |= 0x01
-		}
-		Else {
-			If (DSD0 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0)
-				PMTM = DerefOf(MDRT [Local0])
-			}
-		}
-
-		If (BFFG & 0x04) {	/* Drive 1 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0)
-			PDSM = Local0 % 7
-			PDCR |= 0x02
-		}
-		Else {
-			If (DSD1 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0)
-				PMTS = DerefOf(MDRT [Local0])
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xA0
-			CMDB = 0xA0
-			CMDC = 0xA0
-
-			POMD = PPMM | 0x08
-
-			If (PDCR & 0x01) {
-				DMMD = PDMM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xB0
-			CMDB = 0xB0
-			CMDC = 0xB0
-
-			POMD = PPSM | 0x08
-
-			If (PDCR & 0x02) {
-				DMMD = PDSM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}
diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl
deleted file mode 100644
index b7fd53af8c..0000000000
--- a/src/mainboard/amd/persimmon/acpi/routing.asl
+++ /dev/null
@@ -1,314 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* OHCI, dev 18, 19, 22 func 0
-		 * EHCI, dev 18, 19, 22 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },	/* Dev 12, INTA, handled by INTC device, Global */
-		Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* OHCI, dev 18, 19, 22 func 0
-		 * EHCI, dev 18, 19, 22 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: pcie */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */
-		Package(){0x0003FFFF, 0, 0, 0x14 },
-		Package(){0x0003FFFF, 1, 0, 0x15 },
-		Package(){0x0003FFFF, 2, 0, 0x16 },
-		Package(){0x0003FFFF, 3, 0, 0x17 },
-		Package(){0x0004FFFF, 0, 0, 0x15 },
-		Package(){0x0004FFFF, 1, 0, 0x16 },
-		Package(){0x0004FFFF, 2, 0, 0x17 },
-		Package(){0x0004FFFF, 3, 0, 0x14 },
-		Package(){0x0005FFFF, 0, 0, 0x16 },
-		Package(){0x0005FFFF, 1, 0, 0x17 },
-		Package(){0x0005FFFF, 2, 0, 0x14 },
-		Package(){0x0005FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/amd/persimmon/acpi/sata.asl b/src/mainboard/amd/persimmon/acpi/sata.asl
deleted file mode 100644
index e924b571cd..0000000000
--- a/src/mainboard/amd/persimmon/acpi/sata.asl
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P0IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P1IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P2IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P3IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (\_SB.P0IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			 \_SB.P0PR = 1
-		}
-
-		if (\_SB.P1PR) {
-			if (\_SB.P1IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P1PR = 1
-		}
-
-		if (\_SB.P2PR) {
-			if (\_SB.P2IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P2PR = 1
-		}
-
-		if (\_SB.P3PR) {
-			if (\_SB.P3IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P3PR = 1
-		}
-	}
-}
diff --git a/src/mainboard/amd/persimmon/acpi/sleep.asl b/src/mainboard/amd/persimmon/acpi/sleep.asl
deleted file mode 100644
index 3b6fd02055..0000000000
--- a/src/mainboard/amd/persimmon/acpi/sleep.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Don't allow PCIRST# to reset USB */
-	if (Arg0 == 3){
-		URRE = 0
-	}
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	HPDE = 1
-
-	/* Restore PCIRST# so it resets USB */
-	if (Arg0 == 3){
-		URRE = 1
-	}
-
-	/* Arbitrarily clear PciExpWakeStatus */
-	Local1 = PWST
-	PWST = Local1
-
-	/* if (DeRefOf(WKST [0])) {
-	*	WKST [1] = 0
-	* } else {
-	*	WKST [1] = Arg0
-	* }
-	*/
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/amd/persimmon/acpi/superio.asl b/src/mainboard/amd/persimmon/acpi/superio.asl
deleted file mode 100644
index d2d8a44c23..0000000000
--- a/src/mainboard/amd/persimmon/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* No Super I/O device or functionality yet */
diff --git a/src/mainboard/amd/persimmon/acpi/usb_oc.asl b/src/mainboard/amd/persimmon/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/amd/persimmon/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
-	Sleep(20)
-	CMTI = 0x13
-	GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if (GPB0 == PLC0) {
-				PLC0 = ~PLC0
-				\_SB.PT0D = PLC0
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (GPB1 == PLC1) {
-				PLC1 = ~PLC1
-				\_SB.PT1D = PLC1
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (GPB2 == PLC2) {
-				PLC2 = ~PLC2
-				\_SB.PT2D = PLC2
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (GPB3 == PLC3) {
-				PLC3 = ~PLC3
-				\_SB.PT3D = PLC3
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (GPB4 == PLC4) {
-				PLC4 = ~PLC4
-				\_SB.PT4D = PLC4
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (GPB5 == PLC5) {
-				PLC5 = ~PLC5
-				\_SB.PT5D = PLC5
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (GPB6 == PLC6) {
-				PLC6 = ~PLC6
-				\_SB.PT6D = PLC6
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (GPB7 == PLC7) {
-				PLC7 = ~PLC7
-				\_SB.PT7D = PLC7
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (G8IS == PLC8) {
-				PLC8 = ~PLC8
-				\_SB.PT8D = PLC8
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (G9IS == 0) {
-			\_SB.PT9D = 1
-			}
-		}
-	}
-}
diff --git a/src/mainboard/amd/persimmon/board_info.txt b/src/mainboard/amd/persimmon/board_info.txt
deleted file mode 100644
index 85cb19a9d9..0000000000
--- a/src/mainboard/amd/persimmon/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Board name: DBFT1-00-EVAL-KT (Persimmon)
-Category: eval
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/amd/persimmon/bootblock.c b/src/mainboard/amd/persimmon/bootblock.c
deleted file mode 100644
index 8dca363116..0000000000
--- a/src/mainboard/amd/persimmon/bootblock.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <superio/fintek/common/fintek.h>
-#include <superio/fintek/f81865f/f81865f.h>
-
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
-
-void bootblock_mainboard_early_init(void)
-{
-	fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
deleted file mode 100644
index d8d46d499e..0000000000
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_14_SUPPORT		TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
-
-/* Agesa optional capabilities selection */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
-#define BLDOPT_REMOVE_WHEA			FALSE
-
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
-
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-#define BLDCFG_CFG_GNB_HD_AUDIO			FALSE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
-
-/* Agesa configuration values selection */
-#include <AGESA.h>
-
-/* Include the files that instantiate the configuration definitions */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/* Instantiate all solution relevant data */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/amd/persimmon/cmos.layout b/src/mainboard/amd/persimmon/cmos.layout
deleted file mode 100644
index a11e1dd0e6..0000000000
--- a/src/mainboard/amd/persimmon/cmos.layout
+++ /dev/null
@@ -1,35 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-400	1	e	1	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb
deleted file mode 100644
index 5670118ac5..0000000000
--- a/src/mainboard/amd/persimmon/devicetree.cb
+++ /dev/null
@@ -1,139 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family14
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1510 inherit
-		chip northbridge/amd/agesa/family14
-			device pci 0.0 on end # Root Complex
-			device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
-			device pci 4.0 on end # PCIE P2P bridge on-board NIC
-			device pci 5.0 off end # PCIE P2P bridge
-			device pci 6.0 on end # PCIE P2P bridge PCIe slot
-			device pci 7.0 off end # PCIE P2P bridge
-			device pci 8.0 off end # NB/SB Link P2P bridge
-		end # agesa northbridge
-
-		chip southbridge/amd/cimx/sb800
-			device pci 11.0 on end # SATA
-			device pci 12.0 on end # OHCI USB 0-4
-			device pci 12.2 on end # EHCI USB 0-4
-			device pci 13.0 on end # OHCI USB 5-9
-			device pci 13.2 on end # EHCI USB 5-9
-			device pci 14.0 on end # SM
-			device pci 14.1 on end # IDE	0x439c
-			device pci 14.2 on end # HDA	0x4383
-			device pci 14.3 on # LPC		0x439d
-				chip superio/fintek/f81865f
-					device pnp 4e.0 off		# Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 4e.3 off end			# Parallel Port
-					device pnp 4e.4 off end			# Hardware Monitor
-					device pnp 4e.5 on #  Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-					end
-					device pnp 4e.6 off end			# GPIO
-					device pnp 4e.a off end			# PME
-					device pnp 4e.10 on			# COM1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 4e.11 on			# COM2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-				end # f81865f
-			end #LPC
-			device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-			device pci 14.5 off end # OHCI FS/LS USB
-			device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
-			device pci 15.0 off end # PCIe PortA
-			device pci 15.1 off end # PCIe PortB
-			device pci 15.2 off end # PCIe PortC
-			device pci 15.3 off end # PCIe PortD
-			device pci 16.0 off end # OHCI USB 10-13
-			device pci 16.2 off end # EHCI USB 10-13
-			register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
-			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-
-			#set up SB800 Fan control registers and IMC fan controls
-			register "imc_port_address" = "0x6E"	# 0x2E and 0x6E are common
-			register "fan0_enabled" = "1"
-			register "fan1_enabled" = "1"
-			register "imc_fan_zone0_enabled" = "1"
-			register "imc_fan_zone1_enabled" = "1"
-
-			register "fan0_config_vals" = "{ \
-				FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
-				FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
-			register "fan1_config_vals" = "{ \
-				FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
-				FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
-
-			register "imc_zone0_mode1" = " \
-				IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
-				IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0"
-			register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
-				IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
-			register "imc_zone0_temp_offset" = "0x00"	# No temp offset
-			register "imc_zone0_hysteresis" = "0x05"	# Degrees C Hysteresis
-			register "imc_zone0_smbus_addr" = "0x98"	# Temp Sensor SMBus address
-			register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3"	# SMBUS number
-			register "imc_zone0_pwm_step" = "0x01"		# Fan PWM stepping rate
-			register "imc_zone0_ramping" = "0x00"		# Disable Fan PWM ramping and stepping
-
-			register "imc_zone1_mode1" = " \
-				IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
-				IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1"
-			register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
-				IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
-			register "imc_zone1_temp_offset" = "0x00"	# No temp offset
-			register "imc_zone1_hysteresis" = "0x05"	# Degrees C Hysteresis
-			register "imc_zone1_smbus_addr" = "0x98"	# Temp Sensor SMBus address
-			register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3"	# SMBUS number
-			register "imc_zone1_pwm_step" = "0x01"		# Fan PWM stepping rate
-			register "imc_zone1_ramping" = "0x00"		# Disable Fan PWM ramping and stepping
-
-			# T56N has a Maximum operating temperature  of 90C
-			# ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C
-			# ZONEX_FANSPEEDS - Fan speeds as a "percentage"
-			register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }"
-			register "imc_zone0_fanspeeds"  = "{100,  7,  5,  4,  3, 2, 0, 0 }"
-			register "imc_zone1_thresholds" = "{ 85, 80, 75, 65,  1, 0, 0, 0, 90 }"
-			register "imc_zone1_fanspeeds"  = "{100, 10,  6,  4,  3, 0, 0, 0 }"
-
-		end	#southbridge/amd/cimx/sb800
-
-		chip northbridge/amd/agesa/family14
-
-			# These seem unnecessary
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-			device pci 18.6 on end
-			device pci 18.7 on end
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-
-		end # agesa northbridge
-
-	end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl
deleted file mode 100644
index 834a2cfbf9..0000000000
--- a/src/mainboard/amd/persimmon/dsdt.asl
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	#include <cpu/amd/agesa/family14/acpi/cpu.asl>
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		Device(PCI0) {
-
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
-
-			/* Primary (and only) IDE channel */
-			Device(IDEC) {
-				Name(_ADR, 0x00140001)
-				#include "acpi/ide.asl"
-			} /* end IDEC */
-
-		}
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	#include "acpi/gpe.asl"
-	#include "acpi/usb_oc.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c
deleted file mode 100644
index e5d576a349..0000000000
--- a/src/mainboard/amd/persimmon/irq_tables.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *)(addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* PCI bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum)
-		pirq->checksum = sum;
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
deleted file mode 100644
index 0c60e4dc5a..0000000000
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <device/device.h>
-#include <device/mmio.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/cimx/sb800/pci_devs.h>
-#include <northbridge/amd/agesa/family14/pci_devs.h>
-
-/***********************************************************
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system.  It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair.  These values are chipset and mainboard
- * dependent and should be updated accordingly.
- *
- * These values are used by the PCI configuration space,
- * MP Tables.  TODO: Make ACPI use these values too.
- *
- * The Persimmon PCI INTA/B/C/D pins are connected to
- * FCH pins INTE/F/G/H on the schematic so these need
- * to be routed as well.
- */
-static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
-	/* INTA# - INTH# */
-	[0x00] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0x00, 0xF0, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */
-	[0x10] = 0x1F, 0x1F, 0x1F, 0x0A, 0x1F, 0x1F, 0x1F,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
-	/* USB Devs 18/19/20/22 INTA-C */
-	[0x30] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A,
-	/* IDE, SATA */
-	[0x40] = 0x0B, 0x0B,
-	/* GPPInt0 - 3 */
-	[0x50] = 0x0A, 0x0B, 0x0A, 0x0B
-};
-
-static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
-	/* INTA# - INTH# */
-	[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */
-	[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
-	/* USB Devs 18/19/22/20 INTA-C */
-	[0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12,
-	/* IDE, SATA */
-	[0x40] = 0x11, 0x13,
-	/* GPPInt0 - 3 */
-	[0x50] = 0x10, 0x11, 0x12, 0x13
-};
-
-/*
- * This table defines the index into the picr/intr_data
- * tables for each device.  Any enabled device and slot
- * that uses hardware interrupts should have an entry
- * in this table to define its index into the FCH
- * PCI_INTR register 0xC00/0xC01.  This index will define
- * the interrupt that it should use.  Putting PIRQ_A into
- * the PIN A index for a device will tell that device to
- * use PIC IRQ 10 if it uses PIN A for its hardware INT.
- */
-/*
- * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because PCI INT_PIN swizzling isn't implemented to match
- * the IDSEL (dev 3) of the slot, the table is adjusted for the
- * swizzle and INTA is connected to PIRQH so PINA/B/C/D on
- * off-chip devices should get mapped to PIRQH/E/F/G.
- */
-static const struct pirq_struct mainboard_pirq_data[] = {
-	/* {PCI_devfn,        {PIN A, PIN B, PIN C, PIN D}}, */
-	{GFX_DEVFN,           {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}},      /* VGA:       01.0 */
-	{NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:       04.0 */
-	{NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* PCIe bdg:  06.0 */
-	{SATA_DEVFN,          {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},  /* SATA:      11.0 */
-	{OHCI1_DEVFN,         {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1:     12.0 */
-	{EHCI1_DEVFN,         {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1:     12.2 */
-	{OHCI2_DEVFN,         {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2:     13.0 */
-	{EHCI2_DEVFN,         {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2:     13.2 */
-	{SMBUS_DEVFN,         {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS:     14.0 */
-	{IDE_DEVFN,           {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}},   /* IDE:       14.1 */
-	{HDA_DEVFN,           {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},   /* HDA:       14.2 */
-	{SB_PCI_PORT_DEVFN,   {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}},        /* PCI bdg:   14.4 */
-	{OHCI4_DEVFN,         {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4:     14.5 */
-	{OHCI3_DEVFN,         {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3:     16.0 */
-	{EHCI3_DEVFN,         {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3:     16.2 */
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	pirq_data_ptr = mainboard_pirq_data;
-	pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
-	intr_data_ptr = mainboard_intr_data;
-	picr_data_ptr = mainboard_picr_data;
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	/* enable GPP CLK0 thru CLK1 */
-	/* disable GPP CLK2 thru SLT_GFX_CLK */
-	misc_write8(0, 0xff);
-	misc_write8(1, 0);
-	misc_write8(2, 0);
-	misc_write8(3, 0);
-	misc_write8(4, 0);
-
-	/*
-	 * Initialize ASF registers to an arbitrary address because someone
-	 * long ago set things up this way inside the SPD read code.  The
-	 * SPD read code has been made generic and moved out of the board
-	 * directory, so the ASF init is being done here.
-	 */
-	pm_write8(0x29, 0x80);
-	pm_write8(0x28, 0x61);
-
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h
deleted file mode 100644
index 32c22bcfa1..0000000000
--- a/src/mainboard/amd/persimmon/platform_cfg.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-/**
- * @def BIOS_SIZE
- *      BIOS_SIZE_{1,2,4,8,16}M
- *
- * In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM			0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER			1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
- *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
- *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
- *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
- *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
- *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
- *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
- */
-#define USB_CONFIG		0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL			0x07
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_MODE			CONFIG_SB800_SATA_MODE
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE			0
-#define IDE_NATIVE_MODE			1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_IDE_MODE			IDE_LEGACY_MODE
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK		0x00
-#define INTERNAL_CLOCK		0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED	1
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO			0
-#define AZALIA_DISABLE			1
-#define AZALIA_ENABLE			2
-
-/**
- * @brief INCHIP HDA controller
- */
-#define AZALIA_CONTROLLER		AZALIA_AUTO
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#define AZALIA_PIN_CONFIG		1
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is defined at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is defined at BIT2 & BIT3
- *  SDIN2 is defined at BIT4 & BIT5
- *  SDIN3 is defined at BIT6 & BIT7
- */
-//#define AZALIA_SDIN_PIN		0xAA
-#define AZALIA_SDIN_PIN			0x2A
-
-/**
- * @def GPP_CONTROLLER
- */
-#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#define GPP_CFGMODE			GPP_CFGMODE_X1111
-
-/**
- * @def NB_SB_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define NB_SB_GEN2			TRUE
-
-/**
- * @def SB_GPP_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define SB_GPP_GEN2			TRUE
-
-/**
- * @def SB_GPP_UNHIDE_PORTS
- *    TRUE   - ports visible always, even port empty
- *    FALSE  - ports invisible if port empty
- */
-#define SB_GPP_UNHIDE_PORTS		FALSE
-
-/**
- * @def   GEC_CONFIG
- *    0  - Enable
- *    1  - Disable
- */
-#define GEC_CONFIG			0
-
-static const CODECENTRY persimmon_codec_alc269[] =
-{
-	/* NID, PinConfig */
-	{0x12, 0x411111F0},
-	{0x14, 0x99130110},
-	{0x21, 0x0121401F},
-	{0x17, 0x411111F0},
-	{0x18, 0x01A19820},
-	{0x19, 0x411111F0},
-	{0x1A, 0x0181302F},
-	{0x1B, 0x411111F0},
-	{0x1D, 0x40069E05},
-	{0x1E, 0x411111F0},
-	{0x20, 0x0001FFFF},
-	{0xff, 0xffffffff} /* end of table */
-};
-
-static const CODECTBLLIST codec_tablelist[] =
-{
-	{0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]},
-	{0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL}
-};
-
-/**
- * @def AZALIA_OEM_VERB_TABLE
- *  Mainboard specific codec verb table list
- */
-#define AZALIA_OEM_VERB_TABLE		(&codec_tablelist[0])
-
-#endif /* _PLATFORM_CFG_H_ */
diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c
deleted file mode 100644
index 935e36812f..0000000000
--- a/src/mainboard/amd/south_station/BiosCallOuts.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <amdlib.h>
-#include <amdblocks/acpimmio.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <SB800.h>
-#include <southbridge/amd/cimx/sb800/gpio_oem.h>
-
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GNB_PCIE_SLOT_RESET,		board_GnbPcieSlotReset },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
-	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/* Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS      Status;
-	MEM_DATA_STRUCT   *MemData;
-	UINT32            GpioMmioAddr;
-	UINT8             Data8;
-	UINT8             TempData8;
-
-	MemData = ConfigPtr;
-
-	Status = AGESA_SUCCESS;
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-
-	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	Data8 &= ~BIT5;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
-
-	Data8 |= BIT2 | BIT3;
-	Data8 &= ~BIT4;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
-
-	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	Data8 &= ~BIT5;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
-
-	Data8 |= BIT2 | BIT3;
-	Data8 &= ~BIT4;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
-
-	switch (MemData->ParameterListPtr->DDR3Voltage) {
-	case VOLT1_35:
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_25:
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_5:
-	default:
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-	}
-	return Status;
-}
-
-/* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS           Status;
-	PCIe_SLOT_RESET_INFO   *ResetInfo;
-	UINT32                 GpioMmioAddr;
-	UINT8                  Data8;
-
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-
-	ResetInfo = ConfigPtr;
-	Status = AGESA_UNSUPPORTED;
-	switch (ResetInfo->ResetId) {
-	case 4:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
-			Data8 &= ~(UINT8)BIT6;
-			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
-			Data8 |= BIT6;
-			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	case 6:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
-			Data8 &= ~(UINT8)BIT6;
-			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
-			Data8 |= BIT6;
-			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	case 7:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
-			Data8 &= ~(UINT8)BIT6;
-			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
-			Data8 |= BIT6;
-			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	}
-	return Status;
-}
diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig
deleted file mode 100644
index 32eddb48c9..0000000000
--- a/src/mainboard/amd/south_station/Kconfig
+++ /dev/null
@@ -1,43 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_AMD_SOUTHSTATION
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY14
-	select NORTHBRIDGE_AMD_AGESA_FAMILY14
-	select SOUTHBRIDGE_AMD_CIMX_SB800
-	select SUPERIO_FINTEK_F81865F
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_4096
-	select GFXUMA
-
-config MAINBOARD_DIR
-	default "amd/south_station"
-
-config MAINBOARD_PART_NUMBER
-	default "Southstation"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 4
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS_ID
-	string
-	default "1002,9806"
-
-endif # BOARD_AMD_SOUTHSTATION
diff --git a/src/mainboard/amd/south_station/Kconfig.name b/src/mainboard/amd/south_station/Kconfig.name
deleted file mode 100644
index 0cc745e3bc..0000000000
--- a/src/mainboard/amd/south_station/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_AMD_SOUTHSTATION
-	bool "Southstation"
diff --git a/src/mainboard/amd/south_station/Makefile.inc b/src/mainboard/amd/south_station/Makefile.inc
deleted file mode 100644
index 549801d78f..0000000000
--- a/src/mainboard/amd/south_station/Makefile.inc
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c
deleted file mode 100644
index 339469bb87..0000000000
--- a/src/mainboard/amd/south_station/OemCustomize.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <PlatformMemoryConfiguration.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 4)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 5)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 6)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 7)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	/* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
-	},
-	/* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 VGA */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux1, Hdp1)
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-  NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-  NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
-  PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
diff --git a/src/mainboard/amd/south_station/OptionsIds.h b/src/mainboard/amd/south_station/OptionsIds.h
deleted file mode 100644
index fdd5de0cd1..0000000000
--- a/src/mainboard/amd/south_station/OptionsIds.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-
-#endif
diff --git a/src/mainboard/amd/south_station/acpi/gpe.asl b/src/mainboard/amd/south_station/acpi/gpe.asl
deleted file mode 100644
index 44e7b68eac..0000000000
--- a/src/mainboard/amd/south_station/acpi/gpe.asl
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/amd/south_station/acpi/ide.asl b/src/mainboard/amd/south_station/acpi/ide.asl
deleted file mode 100644
index e3a1bec04e..0000000000
--- a/src/mainboard/amd/south_station/acpi/ide.asl
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Local0 = Arg0 & 0x0F	/* Recovery Width */
-	Local0++
-	Local1 = Arg0 >> 4	/* Command Width */
-	Local1++
-	Return(30 * (Local0 + Local1))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0, Serialized)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If (PPCR & 0x01) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		BFFG |= 0x1A
-
-		PSD0 = GTTM (PPTM) /* save total time of primary PIO master timing  to PIO spd0 */
-		PSD1 = GTTM (PPTS) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If (PDCR & 0x01) {	/* It's under UDMA mode */
-			BFFG |= 0x01
-			DSD0 = DerefOf(UDTT [PDMM])
-		}
-		Else {
-			DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If (PDCR & 0x02) {	/* It's under UDMA mode */
-			BFFG |= 0x04
-			DSD1 = DerefOf(UDTT [PDSM])
-		}
-		Else {
-			DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, Serialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0)
-		PPMM = Local0 % 5 /* Primary PIO master Mode */
-		Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0)
-		PPSM = Local1 % 5 /* Primary PIO slave Mode */
-
-		PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */
-		PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */
-
-		If (BFFG & 0x01) {	/* Drive 0 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0)
-			PDMM = Local0 % 7
-			PDCR |= 0x01
-		}
-		Else {
-			If (DSD0 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0)
-				PMTM = DerefOf(MDRT [Local0])
-			}
-		}
-
-		If (BFFG & 0x04) {	/* Drive 1 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0)
-			PDSM = Local0 % 7
-			PDCR |= 0x02
-		}
-		Else {
-			If (DSD1 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0)
-				PMTS = DerefOf(MDRT [Local0])
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xA0
-			CMDB = 0xA0
-			CMDC = 0xA0
-
-			POMD = PPMM | 0x08
-
-			If (PDCR & 0x01) {
-				DMMD = PDMM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xB0
-			CMDB = 0xB0
-			CMDC = 0xB0
-
-			POMD = PPSM | 0x08
-
-			If (PDCR & 0x02) {
-				DMMD = PDSM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}
diff --git a/src/mainboard/amd/south_station/acpi/routing.asl b/src/mainboard/amd/south_station/acpi/routing.asl
deleted file mode 100644
index 8f8ea45e9e..0000000000
--- a/src/mainboard/amd/south_station/acpi/routing.asl
+++ /dev/null
@@ -1,382 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		Package(){0x0009FFFF, 0, INTB, 0 },
-		Package(){0x0009FFFF, 1, INTC, 0 },
-		Package(){0x0009FFFF, 2, INTD, 0 },
-		Package(){0x0009FFFF, 3, INTA, 0 },
-
-		Package(){0x000AFFFF, 0, INTC, 0 },
-		Package(){0x000AFFFF, 1, INTD, 0 },
-		Package(){0x000AFFFF, 2, INTA, 0 },
-		Package(){0x000AFFFF, 3, INTB, 0 },
-
-		Package(){0x000BFFFF, 0, INTD, 0 },
-		Package(){0x000BFFFF, 1, INTA, 0 },
-		Package(){0x000BFFFF, 2, INTB, 0 },
-		Package(){0x000BFFFF, 3, INTC, 0 },
-
-		Package(){0x000CFFFF, 0, INTA, 0 },
-		Package(){0x000CFFFF, 1, INTB, 0 },
-		Package(){0x000CFFFF, 2, INTC, 0 },
-		Package(){0x000CFFFF, 3, INTD, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 9 - PCIe Bridge for network card */
-		Package(){0x0009FFFF, 0, 0, 17 },
-		Package(){0x0009FFFF, 1, 0, 16 },
-		Package(){0x0009FFFF, 2, 0, 17 },
-		Package(){0x0009FFFF, 3, 0, 18 },
-		/* Bus 0, Dev A - PCIe Bridge for network card */
-		Package(){0x000AFFFF, 0, 0, 18 },
-		Package(){0x000AFFFF, 1, 0, 16 },
-		Package(){0x000AFFFF, 2, 0, 17 },
-		Package(){0x000AFFFF, 3, 0, 18 },
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-		/* Package(){0x0012FFFF, 2, 0, 18 }, */
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-		/* Package(){0x0013FFFF, 2, 0, 16 }, */
-
-		/* Package(){0x00140000, 0, 0, 16 }, */
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: pcie */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-		Package(){0x0007FFFF, 0, 0, 0x16 },
-		Package(){0x0007FFFF, 1, 0, 0x17 },
-		Package(){0x0007FFFF, 2, 0, 0x14 },
-		Package(){0x0007FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/amd/south_station/acpi/sata.asl b/src/mainboard/amd/south_station/acpi/sata.asl
deleted file mode 100644
index e924b571cd..0000000000
--- a/src/mainboard/amd/south_station/acpi/sata.asl
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P0IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P1IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P2IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P3IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (\_SB.P0IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			 \_SB.P0PR = 1
-		}
-
-		if (\_SB.P1PR) {
-			if (\_SB.P1IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P1PR = 1
-		}
-
-		if (\_SB.P2PR) {
-			if (\_SB.P2IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P2PR = 1
-		}
-
-		if (\_SB.P3PR) {
-			if (\_SB.P3IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P3PR = 1
-		}
-	}
-}
diff --git a/src/mainboard/amd/south_station/acpi/sleep.asl b/src/mainboard/amd/south_station/acpi/sleep.asl
deleted file mode 100644
index 3b6fd02055..0000000000
--- a/src/mainboard/amd/south_station/acpi/sleep.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Don't allow PCIRST# to reset USB */
-	if (Arg0 == 3){
-		URRE = 0
-	}
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	HPDE = 1
-
-	/* Restore PCIRST# so it resets USB */
-	if (Arg0 == 3){
-		URRE = 1
-	}
-
-	/* Arbitrarily clear PciExpWakeStatus */
-	Local1 = PWST
-	PWST = Local1
-
-	/* if (DeRefOf(WKST [0])) {
-	*	WKST [1] = 0
-	* } else {
-	*	WKST [1] = Arg0
-	* }
-	*/
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/amd/south_station/acpi/superio.asl b/src/mainboard/amd/south_station/acpi/superio.asl
deleted file mode 100644
index 16990d45f4..0000000000
--- a/src/mainboard/amd/south_station/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/amd/south_station/acpi/usb_oc.asl b/src/mainboard/amd/south_station/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/amd/south_station/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
-	Sleep(20)
-	CMTI = 0x13
-	GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if (GPB0 == PLC0) {
-				PLC0 = ~PLC0
-				\_SB.PT0D = PLC0
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (GPB1 == PLC1) {
-				PLC1 = ~PLC1
-				\_SB.PT1D = PLC1
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (GPB2 == PLC2) {
-				PLC2 = ~PLC2
-				\_SB.PT2D = PLC2
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (GPB3 == PLC3) {
-				PLC3 = ~PLC3
-				\_SB.PT3D = PLC3
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (GPB4 == PLC4) {
-				PLC4 = ~PLC4
-				\_SB.PT4D = PLC4
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (GPB5 == PLC5) {
-				PLC5 = ~PLC5
-				\_SB.PT5D = PLC5
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (GPB6 == PLC6) {
-				PLC6 = ~PLC6
-				\_SB.PT6D = PLC6
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (GPB7 == PLC7) {
-				PLC7 = ~PLC7
-				\_SB.PT7D = PLC7
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (G8IS == PLC8) {
-				PLC8 = ~PLC8
-				\_SB.PT8D = PLC8
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (G9IS == 0) {
-			\_SB.PT9D = 1
-			}
-		}
-	}
-}
diff --git a/src/mainboard/amd/south_station/board_info.txt b/src/mainboard/amd/south_station/board_info.txt
deleted file mode 100644
index 6391228476..0000000000
--- a/src/mainboard/amd/south_station/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Board name: South Station
-Category: eval
-ROM package: SOIC8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/amd/south_station/bootblock.c b/src/mainboard/amd/south_station/bootblock.c
deleted file mode 100644
index 8dca363116..0000000000
--- a/src/mainboard/amd/south_station/bootblock.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <superio/fintek/common/fintek.h>
-#include <superio/fintek/f81865f/f81865f.h>
-
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
-
-void bootblock_mainboard_early_init(void)
-{
-	fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
deleted file mode 100644
index 453102aa6a..0000000000
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_14_SUPPORT		TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
-
-/* Agesa optional capabilities selection */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
-#define BLDOPT_REMOVE_WHEA			TRUE
-
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
-
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-#define BLDCFG_S3_LATE_RESTORE			FALSE
-#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
-
-/* Agesa configuration values selection */
-#include <AGESA.h>
-
-/* Include the files that instantiate the configuration definitions */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/* Instantiate all solution relevant data */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/amd/south_station/cmos.layout b/src/mainboard/amd/south_station/cmos.layout
deleted file mode 100644
index a11e1dd0e6..0000000000
--- a/src/mainboard/amd/south_station/cmos.layout
+++ /dev/null
@@ -1,35 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-400	1	e	1	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb
deleted file mode 100644
index c873e4e904..0000000000
--- a/src/mainboard/amd/south_station/devicetree.cb
+++ /dev/null
@@ -1,89 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family14
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1510 inherit
-		chip northbridge/amd/agesa/family14
-			device pci 0.0 on end # Root Complex
-			device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
-			device pci 1.1 on end # Internal HDMI Audio
-			device pci 4.0 on end # PCIE P2P bridge 0x9604
-			device pci 5.0 on end # PCIE P2P bridge 0x9605
-			device pci 6.0 on end # PCIE P2P bridge 0x9606
-			device pci 7.0 on end # PCIE P2P bridge 0x9607
-			device pci 8.0 on end # NB/SB Link P2P bridge
-		end # agesa northbridge
-
-		chip southbridge/amd/cimx/sb800
-			device pci 11.0 on end # SATA
-			device pci 12.0 on end # USB
-			device pci 12.1 on end # USB
-			device pci 12.2 on end # USB
-			device pci 13.0 on end # USB
-			device pci 13.1 on end # USB
-			device pci 13.2 on end # USB
-			device pci 14.0 on end # SM
-			device pci 14.1 on end # IDE    0x439c
-			device pci 14.2 on end # HDA    0x4383
-			device pci 14.3 on # LPC        0x439d
-				chip superio/fintek/f81865f
-					device pnp 4e.0 off		# Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 4e.3 off end			# Parallel Port
-					device pnp 4e.4 off end			# Hardware Monitor
-					device pnp 4e.5 on #  Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-					end
-					device pnp 4e.6 off end			# GPIO
-					device pnp 4e.a off end			# PME
-					device pnp 4e.10 on			# COM1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 4e.11 off			# COM2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-				end # f81865f
-			end #LPC
-			device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-			device pci 14.5 on  end # USB 2
-			device pci 15.0 off end # PCIe PortA
-			device pci 15.1 off end # PCIe PortB
-			device pci 15.2 off end # PCIe PortC
-			device pci 15.3 off end # PCIe PortD
-			device pci 16.0 off end # OHCI USB3
-			device pci 16.2 off end # EHCI USB3
-			register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
-			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-		end	#southbridge/amd/cimx/sb800
-
-		chip northbridge/amd/agesa/family14
-
-			# These seem unnecessary
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-
-			register "spdAddrLookup" = "
-			{
-			    { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-			    { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-
-		end # agesa northbridge
-
-	end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl
deleted file mode 100644
index 834a2cfbf9..0000000000
--- a/src/mainboard/amd/south_station/dsdt.asl
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	#include <cpu/amd/agesa/family14/acpi/cpu.asl>
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		Device(PCI0) {
-
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
-
-			/* Primary (and only) IDE channel */
-			Device(IDEC) {
-				Name(_ADR, 0x00140001)
-				#include "acpi/ide.asl"
-			} /* end IDEC */
-
-		}
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	#include "acpi/gpe.asl"
-	#include "acpi/usb_oc.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c
deleted file mode 100644
index e5d576a349..0000000000
--- a/src/mainboard/amd/south_station/irq_tables.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *)(addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* PCI bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum)
-		pirq->checksum = sum;
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c
deleted file mode 100644
index e290133d92..0000000000
--- a/src/mainboard/amd/south_station/mainboard.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/acpimmio_legacy_gpio100.h>
-#include <delay.h>
-#include <device/device.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static const u8 mainboard_intr_data[] = {
-	[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,  /* INTA# - INTH# */
-	[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,  /* Misc-nil, 0, 1, 2,  INT from Serial irq */
-	[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x10, 0x11, 0x12, 0x13
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	intr_data_ptr = mainboard_intr_data;
-}
-
-/**
- * Southstation using SB GPIO 17/18 to control the Red/Green LED
- * These two LEDs can be used to show the OS booting status.
- */
-static void southstation_led_init(void)
-{
-	/* multi-function pins switch to GPIO0-35 */
-	pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1);
-
-	/* select IOMux to function2, corresponds to GPIO */
-	iomux_write8(0x11, (iomux_read8(0x11) & 0xfc) | 2);
-	iomux_write8(0x12, (iomux_read8(0x12) & 0xfc) | 2);
-
-	/* Lighting test */
-	gpio_100_write8(0x11, 0x08); //output high
-	gpio_100_write8(0x12, 0x08);
-	mdelay(100);
-	gpio_100_write8(0x11, 0x48); //output low
-	gpio_100_write8(0x12, 0x48);
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	pirq_setup();
-
-	southstation_led_init();
-
-	/*
-	 * Initialize ASF registers to an arbitrary address because someone
-	 * long ago set things up this way inside the SPD read code.  The
-	 * SPD read code has been made generic and moved out of the board
-	 * directory, so the ASF init is being done here.
-	 */
-	pm_write8(0x29, 0x80);
-	pm_write8(0x28, 0x61);
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h
deleted file mode 100644
index 85a60e251b..0000000000
--- a/src/mainboard/amd/south_station/platform_cfg.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-/**
- * @def BIOS_SIZE
- *      BIOS_SIZE_{1,2,4,8,16}M
- *
- * In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM			0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER			1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
- *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
- *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
- *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
- *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
- *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
- *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
- */
-#define USB_CONFIG		0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL			0x1F
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_MODE			CONFIG_SB800_SATA_MODE
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE			0
-#define IDE_NATIVE_MODE			1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_IDE_MODE			IDE_LEGACY_MODE
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK		0x00
-#define INTERNAL_CLOCK		0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED	1
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO			0
-#define AZALIA_DISABLE			1
-#define AZALIA_ENABLE			2
-
-/**
- * @brief INCHIP HDA controller
- */
-#define AZALIA_CONTROLLER		AZALIA_AUTO
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#define AZALIA_PIN_CONFIG		1
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is defined at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is defined at BIT2 & BIT3
- *  SDIN2 is defined at BIT4 & BIT5
- *  SDIN3 is defined at BIT6 & BIT7
- */
-//#define AZALIA_SDIN_PIN		0xAA
-#define AZALIA_SDIN_PIN			0x2A
-
-/**
- * @def GPP_CONTROLLER
- */
-#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#define GPP_CFGMODE			GPP_CFGMODE_X1111
-
-/**
- * @def NB_SB_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define NB_SB_GEN2			TRUE
-
-/**
- * @def SB_GPP_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define SB_GPP_GEN2			TRUE
-
-/**
- * @def SB_GPP_UNHIDE_PORTS
- *    TRUE   - ports visible always, even port empty
- *    FALSE  - ports invisible if port empty
- */
-#define SB_GPP_UNHIDE_PORTS		FALSE
-
-/**
- * @def   GEC_CONFIG
- *    0  - Enable
- *    1  - Disable
- */
-#define GEC_CONFIG			0
-
-#endif
diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c
deleted file mode 100644
index 9fcecbc6cd..0000000000
--- a/src/mainboard/amd/union_station/BiosCallOuts.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <amdlib.h>
-#include <amdblocks/acpimmio.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <SB800.h>
-#include <southbridge/amd/cimx/sb800/gpio_oem.h>
-
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GNB_PCIE_SLOT_RESET,		board_GnbPcieSlotReset },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
-	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/* Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS       Status;
-	MEM_DATA_STRUCT    *MemData;
-	UINT32             GpioMmioAddr;
-	UINT8              Data8;
-	UINT8              TempData8;
-
-	MemData = ConfigPtr;
-
-	Status = AGESA_SUCCESS;
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-
-	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	Data8 &= ~BIT5;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
-
-	Data8 |= BIT2 | BIT3;
-	Data8 &= ~BIT4;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
-
-	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	Data8 &= ~BIT5;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
-
-	Data8 |= BIT2 | BIT3;
-	Data8 &= ~BIT4;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
-
-	switch (MemData->ParameterListPtr->DDR3Voltage) {
-	case VOLT1_35:
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_25:
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_5:
-	default:
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-	}
-	return Status;
-}
-
-/* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS            Status;
-	PCIe_SLOT_RESET_INFO    *ResetInfo;
-	UINT32                  GpioMmioAddr;
-	UINT8                   Data8;
-
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-
-	ResetInfo = ConfigPtr;
-	Status = AGESA_UNSUPPORTED;
-	switch (ResetInfo->ResetId) {
-	case 4:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
-			Data8 &= ~(UINT8)BIT6;
-			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
-			Data8 |= BIT6;
-			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	case 6:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
-			Data8 &= ~(UINT8)BIT6;
-			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
-			Data8 |= BIT6;
-			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	case 7:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
-			Data8 &= ~(UINT8)BIT6;
-			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
-			Data8 |= BIT6;
-			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	}
-	return Status;
-}
diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig
deleted file mode 100644
index 0c20e5fecb..0000000000
--- a/src/mainboard/amd/union_station/Kconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_AMD_UNIONSTATION
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY14
-	select NORTHBRIDGE_AMD_AGESA_FAMILY14
-	select SOUTHBRIDGE_AMD_CIMX_SB800
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_2048
-	select GFXUMA
-
-config MAINBOARD_DIR
-	default "amd/union_station"
-
-config MAINBOARD_PART_NUMBER
-	default "Unionstation"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 4
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS_ID
-	string
-	default "1002,9802"
-
-endif # BOARD_AMD_UNIONSTATION
diff --git a/src/mainboard/amd/union_station/Kconfig.name b/src/mainboard/amd/union_station/Kconfig.name
deleted file mode 100644
index 9af3c8270b..0000000000
--- a/src/mainboard/amd/union_station/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_AMD_UNIONSTATION
-	bool "Unionstation"
diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc
deleted file mode 100644
index 549801d78f..0000000000
--- a/src/mainboard/amd/union_station/Makefile.inc
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c
deleted file mode 100644
index 16b2db2425..0000000000
--- a/src/mainboard/amd/union_station/OemCustomize.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <PlatformMemoryConfiguration.h>
-#include <northbridge/amd/agesa/state_machine.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 4)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 5)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 6)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 7)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
-	},
-	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-  NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-  NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
-  PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
diff --git a/src/mainboard/amd/union_station/OptionsIds.h b/src/mainboard/amd/union_station/OptionsIds.h
deleted file mode 100644
index fdd5de0cd1..0000000000
--- a/src/mainboard/amd/union_station/OptionsIds.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-
-#endif
diff --git a/src/mainboard/amd/union_station/acpi/gpe.asl b/src/mainboard/amd/union_station/acpi/gpe.asl
deleted file mode 100644
index 44e7b68eac..0000000000
--- a/src/mainboard/amd/union_station/acpi/gpe.asl
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/amd/union_station/acpi/ide.asl b/src/mainboard/amd/union_station/acpi/ide.asl
deleted file mode 100644
index e3a1bec04e..0000000000
--- a/src/mainboard/amd/union_station/acpi/ide.asl
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Local0 = Arg0 & 0x0F	/* Recovery Width */
-	Local0++
-	Local1 = Arg0 >> 4	/* Command Width */
-	Local1++
-	Return(30 * (Local0 + Local1))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0, Serialized)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If (PPCR & 0x01) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		BFFG |= 0x1A
-
-		PSD0 = GTTM (PPTM) /* save total time of primary PIO master timing  to PIO spd0 */
-		PSD1 = GTTM (PPTS) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If (PDCR & 0x01) {	/* It's under UDMA mode */
-			BFFG |= 0x01
-			DSD0 = DerefOf(UDTT [PDMM])
-		}
-		Else {
-			DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If (PDCR & 0x02) {	/* It's under UDMA mode */
-			BFFG |= 0x04
-			DSD1 = DerefOf(UDTT [PDSM])
-		}
-		Else {
-			DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, Serialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0)
-		PPMM = Local0 % 5 /* Primary PIO master Mode */
-		Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0)
-		PPSM = Local1 % 5 /* Primary PIO slave Mode */
-
-		PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */
-		PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */
-
-		If (BFFG & 0x01) {	/* Drive 0 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0)
-			PDMM = Local0 % 7
-			PDCR |= 0x01
-		}
-		Else {
-			If (DSD0 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0)
-				PMTM = DerefOf(MDRT [Local0])
-			}
-		}
-
-		If (BFFG & 0x04) {	/* Drive 1 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0)
-			PDSM = Local0 % 7
-			PDCR |= 0x02
-		}
-		Else {
-			If (DSD1 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0)
-				PMTS = DerefOf(MDRT [Local0])
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xA0
-			CMDB = 0xA0
-			CMDC = 0xA0
-
-			POMD = PPMM | 0x08
-
-			If (PDCR & 0x01) {
-				DMMD = PDMM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xB0
-			CMDB = 0xB0
-			CMDC = 0xB0
-
-			POMD = PPSM | 0x08
-
-			If (PDCR & 0x02) {
-				DMMD = PDSM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}
diff --git a/src/mainboard/amd/union_station/acpi/routing.asl b/src/mainboard/amd/union_station/acpi/routing.asl
deleted file mode 100644
index 8f8ea45e9e..0000000000
--- a/src/mainboard/amd/union_station/acpi/routing.asl
+++ /dev/null
@@ -1,382 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		Package(){0x0009FFFF, 0, INTB, 0 },
-		Package(){0x0009FFFF, 1, INTC, 0 },
-		Package(){0x0009FFFF, 2, INTD, 0 },
-		Package(){0x0009FFFF, 3, INTA, 0 },
-
-		Package(){0x000AFFFF, 0, INTC, 0 },
-		Package(){0x000AFFFF, 1, INTD, 0 },
-		Package(){0x000AFFFF, 2, INTA, 0 },
-		Package(){0x000AFFFF, 3, INTB, 0 },
-
-		Package(){0x000BFFFF, 0, INTD, 0 },
-		Package(){0x000BFFFF, 1, INTA, 0 },
-		Package(){0x000BFFFF, 2, INTB, 0 },
-		Package(){0x000BFFFF, 3, INTC, 0 },
-
-		Package(){0x000CFFFF, 0, INTA, 0 },
-		Package(){0x000CFFFF, 1, INTB, 0 },
-		Package(){0x000CFFFF, 2, INTC, 0 },
-		Package(){0x000CFFFF, 3, INTD, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 9 - PCIe Bridge for network card */
-		Package(){0x0009FFFF, 0, 0, 17 },
-		Package(){0x0009FFFF, 1, 0, 16 },
-		Package(){0x0009FFFF, 2, 0, 17 },
-		Package(){0x0009FFFF, 3, 0, 18 },
-		/* Bus 0, Dev A - PCIe Bridge for network card */
-		Package(){0x000AFFFF, 0, 0, 18 },
-		Package(){0x000AFFFF, 1, 0, 16 },
-		Package(){0x000AFFFF, 2, 0, 17 },
-		Package(){0x000AFFFF, 3, 0, 18 },
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-		/* Package(){0x0012FFFF, 2, 0, 18 }, */
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-		/* Package(){0x0013FFFF, 2, 0, 16 }, */
-
-		/* Package(){0x00140000, 0, 0, 16 }, */
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: pcie */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-		Package(){0x0007FFFF, 0, 0, 0x16 },
-		Package(){0x0007FFFF, 1, 0, 0x17 },
-		Package(){0x0007FFFF, 2, 0, 0x14 },
-		Package(){0x0007FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/amd/union_station/acpi/sata.asl b/src/mainboard/amd/union_station/acpi/sata.asl
deleted file mode 100644
index e924b571cd..0000000000
--- a/src/mainboard/amd/union_station/acpi/sata.asl
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P0IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P1IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P2IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P3IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (\_SB.P0IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			 \_SB.P0PR = 1
-		}
-
-		if (\_SB.P1PR) {
-			if (\_SB.P1IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P1PR = 1
-		}
-
-		if (\_SB.P2PR) {
-			if (\_SB.P2IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P2PR = 1
-		}
-
-		if (\_SB.P3PR) {
-			if (\_SB.P3IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P3PR = 1
-		}
-	}
-}
diff --git a/src/mainboard/amd/union_station/acpi/sleep.asl b/src/mainboard/amd/union_station/acpi/sleep.asl
deleted file mode 100644
index 3b6fd02055..0000000000
--- a/src/mainboard/amd/union_station/acpi/sleep.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Don't allow PCIRST# to reset USB */
-	if (Arg0 == 3){
-		URRE = 0
-	}
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	HPDE = 1
-
-	/* Restore PCIRST# so it resets USB */
-	if (Arg0 == 3){
-		URRE = 1
-	}
-
-	/* Arbitrarily clear PciExpWakeStatus */
-	Local1 = PWST
-	PWST = Local1
-
-	/* if (DeRefOf(WKST [0])) {
-	*	WKST [1] = 0
-	* } else {
-	*	WKST [1] = Arg0
-	* }
-	*/
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/amd/union_station/acpi/superio.asl b/src/mainboard/amd/union_station/acpi/superio.asl
deleted file mode 100644
index 16990d45f4..0000000000
--- a/src/mainboard/amd/union_station/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/amd/union_station/acpi/usb_oc.asl b/src/mainboard/amd/union_station/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/amd/union_station/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
-	Sleep(20)
-	CMTI = 0x13
-	GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if (GPB0 == PLC0) {
-				PLC0 = ~PLC0
-				\_SB.PT0D = PLC0
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (GPB1 == PLC1) {
-				PLC1 = ~PLC1
-				\_SB.PT1D = PLC1
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (GPB2 == PLC2) {
-				PLC2 = ~PLC2
-				\_SB.PT2D = PLC2
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (GPB3 == PLC3) {
-				PLC3 = ~PLC3
-				\_SB.PT3D = PLC3
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (GPB4 == PLC4) {
-				PLC4 = ~PLC4
-				\_SB.PT4D = PLC4
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (GPB5 == PLC5) {
-				PLC5 = ~PLC5
-				\_SB.PT5D = PLC5
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (GPB6 == PLC6) {
-				PLC6 = ~PLC6
-				\_SB.PT6D = PLC6
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (GPB7 == PLC7) {
-				PLC7 = ~PLC7
-				\_SB.PT7D = PLC7
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (G8IS == PLC8) {
-				PLC8 = ~PLC8
-				\_SB.PT8D = PLC8
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (G9IS == 0) {
-			\_SB.PT9D = 1
-			}
-		}
-	}
-}
diff --git a/src/mainboard/amd/union_station/board_info.txt b/src/mainboard/amd/union_station/board_info.txt
deleted file mode 100644
index 23fc323460..0000000000
--- a/src/mainboard/amd/union_station/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Board name: Union Station
-Category: eval
-ROM package: SOIC8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/amd/union_station/bootblock.c b/src/mainboard/amd/union_station/bootblock.c
deleted file mode 100644
index ccd8ec1b40..0000000000
--- a/src/mainboard/amd/union_station/bootblock.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-
-void bootblock_mainboard_early_init(void)
-{
-}
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
deleted file mode 100644
index 453102aa6a..0000000000
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_14_SUPPORT		TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
-
-/* Agesa optional capabilities selection */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
-#define BLDOPT_REMOVE_WHEA			TRUE
-
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
-
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-#define BLDCFG_S3_LATE_RESTORE			FALSE
-#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
-
-/* Agesa configuration values selection */
-#include <AGESA.h>
-
-/* Include the files that instantiate the configuration definitions */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/* Instantiate all solution relevant data */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/amd/union_station/cmos.layout b/src/mainboard/amd/union_station/cmos.layout
deleted file mode 100644
index a11e1dd0e6..0000000000
--- a/src/mainboard/amd/union_station/cmos.layout
+++ /dev/null
@@ -1,35 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-400	1	e	1	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb
deleted file mode 100644
index 6c88931d17..0000000000
--- a/src/mainboard/amd/union_station/devicetree.cb
+++ /dev/null
@@ -1,65 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family14
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1510 inherit
-		chip northbridge/amd/agesa/family14
-			device pci 0.0 on end # Root Complex
-			device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
-			device pci 1.1 on end # Internal HDMI Audio
-			device pci 4.0 on end # PCIE P2P bridge 0x9604
-			device pci 5.0 on end # PCIE P2P bridge 0x9605
-			device pci 6.0 on end # PCIE P2P bridge 0x9606
-			device pci 7.0 on end # PCIE P2P bridge 0x9607
-			device pci 8.0 on end # NB/SB Link P2P bridge
-		end # agesa northbridge
-
-		chip southbridge/amd/cimx/sb800
-			device pci 11.0 on end # SATA
-			device pci 12.0 on end # USB
-			device pci 12.1 on end # USB
-			device pci 12.2 on end # USB
-			device pci 13.0 on end # USB
-			device pci 13.1 on end # USB
-			device pci 13.2 on end # USB
-			device pci 14.0 on end # SM
-			device pci 14.1 on end # IDE    0x439c
-			device pci 14.2 on end # HDA    0x4383
-			device pci 14.3 on end # LPC        0x439d
-			device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-			device pci 14.5 on  end # USB 2
-			device pci 15.0 off end # PCIe PortA
-			device pci 15.1 off end # PCIe PortB
-			device pci 15.2 off end # PCIe PortC
-			device pci 15.3 off end # PCIe PortD
-			device pci 16.0 off end # OHCI USB3
-			device pci 16.2 off end # EHCI USB3
-			register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
-			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-		end	#southbridge/amd/cimx/sb800
-
-		chip northbridge/amd/agesa/family14
-
-			# These seem unnecessary
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-
-			register "spdAddrLookup" = "
-			{
-			    { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-			    { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-
-		end # agesa northbridge
-
-	end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl
deleted file mode 100644
index 834a2cfbf9..0000000000
--- a/src/mainboard/amd/union_station/dsdt.asl
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	#include <cpu/amd/agesa/family14/acpi/cpu.asl>
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		Device(PCI0) {
-
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
-
-			/* Primary (and only) IDE channel */
-			Device(IDEC) {
-				Name(_ADR, 0x00140001)
-				#include "acpi/ide.asl"
-			} /* end IDEC */
-
-		}
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	#include "acpi/gpe.asl"
-	#include "acpi/usb_oc.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c
deleted file mode 100644
index e5d576a349..0000000000
--- a/src/mainboard/amd/union_station/irq_tables.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *)(addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* PCI bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum)
-		pirq->checksum = sum;
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c
deleted file mode 100644
index 9850a9056f..0000000000
--- a/src/mainboard/amd/union_station/mainboard.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <device/device.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static const u8 mainboard_intr_data[] = {
-	[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,  /* INTA# - INTH# */
-	[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,  /* Misc-nil, 0, 1, 2,  INT from Serial irq */
-	[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x10, 0x11, 0x12, 0x13
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	intr_data_ptr = mainboard_intr_data;
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	pirq_setup();
-
-	/*
-	 * Initialize ASF registers to an arbitrary address because someone
-	 * long ago set things up this way inside the SPD read code.  The
-	 * SPD read code has been made generic and moved out of the board
-	 * directory, so the ASF init is being done here.
-	 */
-	pm_write8(0x29, 0x80);
-	pm_write8(0x28, 0x61);
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h
deleted file mode 100644
index 85a60e251b..0000000000
--- a/src/mainboard/amd/union_station/platform_cfg.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-/**
- * @def BIOS_SIZE
- *      BIOS_SIZE_{1,2,4,8,16}M
- *
- * In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM			0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER			1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
- *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
- *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
- *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
- *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
- *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
- *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
- */
-#define USB_CONFIG		0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL			0x1F
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_MODE			CONFIG_SB800_SATA_MODE
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE			0
-#define IDE_NATIVE_MODE			1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_IDE_MODE			IDE_LEGACY_MODE
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK		0x00
-#define INTERNAL_CLOCK		0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED	1
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO			0
-#define AZALIA_DISABLE			1
-#define AZALIA_ENABLE			2
-
-/**
- * @brief INCHIP HDA controller
- */
-#define AZALIA_CONTROLLER		AZALIA_AUTO
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#define AZALIA_PIN_CONFIG		1
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is defined at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is defined at BIT2 & BIT3
- *  SDIN2 is defined at BIT4 & BIT5
- *  SDIN3 is defined at BIT6 & BIT7
- */
-//#define AZALIA_SDIN_PIN		0xAA
-#define AZALIA_SDIN_PIN			0x2A
-
-/**
- * @def GPP_CONTROLLER
- */
-#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#define GPP_CFGMODE			GPP_CFGMODE_X1111
-
-/**
- * @def NB_SB_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define NB_SB_GEN2			TRUE
-
-/**
- * @def SB_GPP_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define SB_GPP_GEN2			TRUE
-
-/**
- * @def SB_GPP_UNHIDE_PORTS
- *    TRUE   - ports visible always, even port empty
- *    FALSE  - ports invisible if port empty
- */
-#define SB_GPP_UNHIDE_PORTS		FALSE
-
-/**
- * @def   GEC_CONFIG
- *    0  - Enable
- *    1  - Disable
- */
-#define GEC_CONFIG			0
-
-#endif