diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-12-15 10:57:30 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-16 20:14:34 +0000 |
| commit | d123f8d8716811149ecdf7d51661d8cee6f48577 (patch) | |
| tree | 36c6ae14a65508adac7889c4d43fa098db0bafca /src/mainboard/amd | |
| parent | 1c295092d61c2ac7427ddac6d194d99337f86094 (diff) | |
soc/amd/genoa: rename to genoa_poc
Even though this SoC is called 'Genoa', the openSIL implementation and
the corresponding coreboot integration is only a proof of concept that
isn't fully featured, has known limitations and bugs, and is not meant
for or ready to being productized. Adding the proof of concept suffix to
the name should point this out clearly enough so that no potential
customer could infer that this might be a fully functional and supported
implementation which it is not.
Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/onyx/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/onyx/devicetree.cb | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/amd/onyx/Kconfig b/src/mainboard/amd/onyx/Kconfig index e724d14ab0..7224a9b662 100644 --- a/src/mainboard/amd/onyx/Kconfig +++ b/src/mainboard/amd/onyx/Kconfig @@ -2,7 +2,7 @@ if BOARD_AMD_ONYX config BOARD_SPECIFIC_OPTIONS def_bool y - select SOC_AMD_GENOA + select SOC_AMD_GENOA_POC select BOARD_ROMSIZE_KB_32768 select AMD_SOC_CONSOLE_UART diff --git a/src/mainboard/amd/onyx/devicetree.cb b/src/mainboard/amd/onyx/devicetree.cb index d53da0ed1f..a18eff40da 100644 --- a/src/mainboard/amd/onyx/devicetree.cb +++ b/src/mainboard/amd/onyx/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/amd/genoa +chip soc/amd/genoa_poc # USB configuration register "usb.xhci0_enable" = "1" |