AGESA boards: Use devicetree for PCI bus enumeration

Previously MP table contained PCI_INT entries for PCI bus behind bridge
0:14.4 even if said PCI bridge function was disabled.
Remove these as invalid, indeterminate bus number could cause conflicts.

PCI_INT entries with bus_sb800[2], bus_hudson[2] and bus_yangtze[2]
were invalid as there is no PCI bridge hardware on device 0:14.0.
Remove these as invalid, indeterminate bus number could cause conflicts.

Change-Id: Ie6a3807f64c8651cf9f732612e1aa7f376a3134f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6358
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

9 files changed, 179 insertions, 192 deletions

diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c
index d239a7e749..4e481f51b6 100644
--- a/src/mainboard/amd/dinar/mptable.c
+++ b/src/mainboard/amd/dinar/mptable.c
@@ -28,8 +28,6 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/amd/amdfam15.h>
 
-extern u8 bus_sb700[2];
-
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
@@ -126,24 +124,28 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
 
 	/* PCI slots */
-	/* PCI_SLOT 0. */
-	PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
-	PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
-	PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
-	PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
-
-	/* PCI_SLOT 1. */
-	PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
-	PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
-	PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
-	PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
-
-	/* PCI_SLOT 2. */
-	PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
-	PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
-	PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
-	PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
-
+	dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	if (dev && dev->enabled) {
+		u8 bus_pci = dev->link_list->secondary;
+
+		/* PCI_SLOT 0. */
+		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+		/* PCI_SLOT 1. */
+		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+		/* PCI_SLOT 2. */
+		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+	}
 
 	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 	IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index cfe1837c5b..4a57d3c002 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -27,11 +27,8 @@
 #include <cpu/amd/amdfam14.h>
 #include <SBPLATFORM.h>
 
-extern u8 bus_sb800[6];
-
 extern u32 apicid_sb800;
 
-
 u8 intr_data[] = {
 	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
 	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -108,27 +105,27 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	/* PCI_SLOT 0. */
-	PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
-	PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
-	PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
-	PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
-	/* PCI_SLOT 1. */
-	PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
-	PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
-	PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
-	PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
-	/* PCI_SLOT 2. */
-	PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
-	PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
-	PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
-	PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
-	PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
-	PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
-	PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	if (dev && dev->enabled) {
+		u8 bus_pci = dev->link_list->secondary;
+		/* PCI_SLOT 0. */
+		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+		/* PCI_SLOT 1. */
+		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+		/* PCI_SLOT 2. */
+		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+	}
 
 	/* PCIe PortA */
 	PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index 4a4b15dabb..c06863b1a7 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -29,8 +29,6 @@
 #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
 
 #define IO_APIC_ID    CONFIG_MAX_CPUS
-extern u8 bus_yangtze[6];
-
 extern u32 apicid_yangtze;
 
 u8 picr_data[0x54] = {
@@ -189,27 +187,27 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	/* PCI_SLOT 0. */
-	PCI_INT(bus_yangtze[1], 0x5, 0x0, 0x14);
-	PCI_INT(bus_yangtze[1], 0x5, 0x1, 0x15);
-	PCI_INT(bus_yangtze[1], 0x5, 0x2, 0x16);
-	PCI_INT(bus_yangtze[1], 0x5, 0x3, 0x17);
-
-	/* PCI_SLOT 1. */
-	PCI_INT(bus_yangtze[1], 0x6, 0x0, 0x15);
-	PCI_INT(bus_yangtze[1], 0x6, 0x1, 0x16);
-	PCI_INT(bus_yangtze[1], 0x6, 0x2, 0x17);
-	PCI_INT(bus_yangtze[1], 0x6, 0x3, 0x14);
-
-	/* PCI_SLOT 2. */
-	PCI_INT(bus_yangtze[1], 0x7, 0x0, 0x16);
-	PCI_INT(bus_yangtze[1], 0x7, 0x1, 0x17);
-	PCI_INT(bus_yangtze[1], 0x7, 0x2, 0x14);
-	PCI_INT(bus_yangtze[1], 0x7, 0x3, 0x15);
-
-	PCI_INT(bus_yangtze[2], 0x0, 0x0, 0x12);
-	PCI_INT(bus_yangtze[2], 0x0, 0x1, 0x13);
-	PCI_INT(bus_yangtze[2], 0x0, 0x2, 0x14);
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	if (dev && dev->enabled) {
+		u8 bus_pci = dev->link_list->secondary;
+		/* PCI_SLOT 0. */
+		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+		/* PCI_SLOT 1. */
+		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+		/* PCI_SLOT 2. */
+		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+	}
 
 	/* PCIe Lan*/
 	PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index 06c179168e..2f5179f56a 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -29,8 +29,6 @@
 #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
 
 #define IO_APIC_ID    CONFIG_MAX_CPUS
-extern u8 bus_hudson[6];
-
 extern u32 apicid_hudson;
 
 u8 picr_data[0x54] = {
@@ -150,27 +148,27 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	/* PCI_SLOT 0. */
-	PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
-	PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
-	PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
-	PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
-
-	/* PCI_SLOT 1. */
-	PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15);
-	PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16);
-	PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17);
-	PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14);
-
-	/* PCI_SLOT 2. */
-	PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16);
-	PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17);
-	PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14);
-	PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15);
-
-	PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
-	PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
-	PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	if (dev && dev->enabled) {
+		u8 bus_pci = dev->link_list->secondary;
+		/* PCI_SLOT 0. */
+		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+		/* PCI_SLOT 1. */
+		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+		/* PCI_SLOT 2. */
+		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+	}
 
 	/* PCIe Lan*/
 	PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 1c7e86a1d6..0d5f5ce931 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -31,11 +31,9 @@
 #include <drivers/generic/ioapic/chip.h>
 #include <arch/ioapic.h>
 
-extern u8 bus_sb800[6];
 extern u32 apicid_sb800;
 extern u32 apicver_sb800;
 
-
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
@@ -110,11 +108,15 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]);	/* Use INTE */
 
 	/* PCI slots */
-	/* PCI_SLOT 0 */
-	PCI_INT(bus_sb800[1], 0x5, 0x0, intr_data_ptr[PIRQ_E]);	/* INTA -> INTE */
-	PCI_INT(bus_sb800[1], 0x5, 0x1, intr_data_ptr[PIRQ_F]);	/* INTB -> INTF */
-	PCI_INT(bus_sb800[1], 0x5, 0x2, intr_data_ptr[PIRQ_G]);	/* INTC -> INTG */
-	PCI_INT(bus_sb800[1], 0x5, 0x3, intr_data_ptr[PIRQ_H]);	/* INTD -> INTH */
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	if (dev && dev->enabled) {
+		u8 bus_pci = dev->link_list->secondary;
+		/* PCI_SLOT 0 */
+		PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);	/* INTA -> INTE */
+		PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);	/* INTB -> INTF */
+		PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);	/* INTC -> INTG */
+		PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);	/* INTD -> INTH */
+	}
 
 	/* PCIe PortA */
 	PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]);	/* INTA -> INTE */
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index 32af39a7b5..57eaa0ec3a 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -27,11 +27,8 @@
 #include <cpu/amd/amdfam14.h>
 #include <SBPLATFORM.h>
 
-extern u8 bus_sb800[6];
-
 extern u32 apicid_sb800;
 
-
 u8 intr_data[] = {
   [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
   [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -104,27 +101,27 @@ static void *smp_write_config_table(void *v)
   /* on board NIC & Slot PCIE.  */
 
   /* PCI slots */
-  /* PCI_SLOT 0. */
-  PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
-  PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
-  PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
-  PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
-  /* PCI_SLOT 1. */
-  PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
-  PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
-  PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
-  PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
-  /* PCI_SLOT 2. */
-  PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
-  PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
-  PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
-  PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
-  PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
-  PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
-  PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	if (dev && dev->enabled) {
+		u8 bus_pci = dev->link_list->secondary;
+		/* PCI_SLOT 0. */
+		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+		/* PCI_SLOT 1. */
+		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+		/* PCI_SLOT 2. */
+		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+	}
 
   /* PCIe PortA */
   PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index 089d260c20..7f9aa7c4b2 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -29,8 +29,6 @@
 #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
 
 #define IO_APIC_ID    CONFIG_MAX_CPUS
-extern u8 bus_hudson[6];
-
 extern u32 apicid_hudson;
 
 u8 picr_data[] = {
@@ -150,27 +148,27 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	/* PCI_SLOT 0. */
-	PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
-	PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
-	PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
-	PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
-
-	/* PCI_SLOT 1. */
-	PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15);
-	PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16);
-	PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17);
-	PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14);
-
-	/* PCI_SLOT 2. */
-	PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16);
-	PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17);
-	PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14);
-	PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15);
-
-	PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
-	PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
-	PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	if (dev && dev->enabled) {
+		u8 bus_pci = dev->link_list->secondary;
+		/* PCI_SLOT 0. */
+		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+		/* PCI_SLOT 1. */
+		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+		/* PCI_SLOT 2. */
+		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+	}
 
 	/* PCIe Lan*/
 	PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index a9236eda7d..477d97adbf 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -30,9 +30,6 @@
 #include "SbPlatform.h"
 
 #define IO_APIC_ID    CONFIG_MAX_CPUS
-extern u8 bus_sb900[6];
-
-
 u32 apicid_sb900;
 
 u8 picr_data[] = {
@@ -189,27 +186,28 @@ static void *smp_write_config_table(void *v)
   /* on board NIC & Slot PCIE.  */
 
   /* PCI slots */
-  /* PCI_SLOT 0. */
-  PCI_INT(bus_sb900[1], 0x5, 0x0, 0x14);
-  PCI_INT(bus_sb900[1], 0x5, 0x1, 0x15);
-  PCI_INT(bus_sb900[1], 0x5, 0x2, 0x16);
-  PCI_INT(bus_sb900[1], 0x5, 0x3, 0x17);
-
-  /* PCI_SLOT 1. */
-  PCI_INT(bus_sb900[1], 0x6, 0x0, 0x15);
-  PCI_INT(bus_sb900[1], 0x6, 0x1, 0x16);
-  PCI_INT(bus_sb900[1], 0x6, 0x2, 0x17);
-  PCI_INT(bus_sb900[1], 0x6, 0x3, 0x14);
-
-  /* PCI_SLOT 2. */
-  PCI_INT(bus_sb900[1], 0x7, 0x0, 0x16);
-  PCI_INT(bus_sb900[1], 0x7, 0x1, 0x17);
-  PCI_INT(bus_sb900[1], 0x7, 0x2, 0x14);
-  PCI_INT(bus_sb900[1], 0x7, 0x3, 0x15);
-
-  PCI_INT(bus_sb900[1], 0x0, 0x0, 0x12);
-  PCI_INT(bus_sb900[1], 0x0, 0x1, 0x13);
-  PCI_INT(bus_sb900[1], 0x0, 0x2, 0x14);
+  device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+  if (dev && dev->enabled) {
+	  u8 bus_pci = dev->link_list->secondary;
+
+	  /* PCI_SLOT 0. */
+	  PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+	  PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+	  PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+	  PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+	  /* PCI_SLOT 1. */
+	  PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+	  PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+	  PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+	  PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+	  /* PCI_SLOT 2. */
+	  PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+	  PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+	  PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+	  PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+  }
 
   /* PCIe Lan*/
   PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index 32af39a7b5..57eaa0ec3a 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -27,11 +27,8 @@
 #include <cpu/amd/amdfam14.h>
 #include <SBPLATFORM.h>
 
-extern u8 bus_sb800[6];
-
 extern u32 apicid_sb800;
 
-
 u8 intr_data[] = {
   [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
   [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -104,27 +101,27 @@ static void *smp_write_config_table(void *v)
   /* on board NIC & Slot PCIE.  */
 
   /* PCI slots */
-  /* PCI_SLOT 0. */
-  PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
-  PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
-  PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
-  PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
-  /* PCI_SLOT 1. */
-  PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
-  PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
-  PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
-  PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
-  /* PCI_SLOT 2. */
-  PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
-  PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
-  PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
-  PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
-  PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
-  PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
-  PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	if (dev && dev->enabled) {
+		u8 bus_pci = dev->link_list->secondary;
+		/* PCI_SLOT 0. */
+		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+		/* PCI_SLOT 1. */
+		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+		/* PCI_SLOT 2. */
+		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+	}
 
   /* PCIe PortA */
   PCI_INT(0x0, 0x15, 0x0, 0x10);