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authorMarc Jones <marcj303@gmail.com>2009-05-14 23:42:41 +0000
committerMarc Jones <marc.jones@amd.com>2009-05-14 23:42:41 +0000
commit99fd2a3b3ac587498b551c2c6e5d6d20f646e65b (patch)
tree2c82d99a8b7ec6162393ec5dd5003f22e4d2f269 /src/mainboard/amd
parent9ea1e0c18a44abb17497a30557a61dda25ec2922 (diff)
Update equivalent processor revision ID to load latest microcode patches and
register setting for all FAM10 processors. This does not include new errata for FAM10 C2. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Vincent Lim (vincent.lim@amd.com) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/serengeti_cheetah_fam10/Options.lb9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
index 8bf43bb656..80dff3a67a 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
@@ -261,11 +261,12 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
##
## Set microcode patch file name
##
-## Barcelona rev Ax: "mc_patch_01000020.h"
-## Barcelona rev B0, B1, BA: "mc_patch_01000084.h"
-## Barcelona rev B2, B3: "mc_patch_01000083.h"
+## Barcelona rev DR-Ax: "mc_patch_01000020.h"
+## Barcelona rev DR-B0, B1, BA: "mc_patch_01000096.h"
+## Barcelona rev DR-B2, B3: "mc_patch_01000095.h"
+## Shanghai rev DA-C2: "mc_patch_0100009f.h"
##
-default AMD_UCODE_PATCH_FILE="mc_patch_01000083.h"
+default AMD_UCODE_PATCH_FILE="mc_patch_01000095.h"
###
### coreboot layout values