diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2011-10-31 12:56:45 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-11-01 19:07:45 +0100 |
| commit | 5ff7c13e858a31addf1558731a12cf6c753b576d (patch) | |
| tree | 82ed6cf7b45f3a86c2c43ab87383355ed6012d6c /src/mainboard/amd | |
| parent | 784544b934d67dc85ccfcf33e04ff148045836ad (diff) | |
remove trailing whitespace
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/amd')
48 files changed, 325 insertions, 325 deletions
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 7dcdd96098..a72f96b4c3 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #include "agesawrapper.h" #include "amdlib.h" #include "BiosCallOuts.h" @@ -58,11 +58,11 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] = {AGESA_GET_IDS_INIT_DATA, BiosGetIdsInitData }, - + {AGESA_HOOKBEFORE_DQS_TRAINING, BiosHookBeforeDQSTraining }, - + {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, @@ -210,7 +210,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points to the end of the allocated nodes list. */ - + } /* Find the node that best fits the requested buffer size */ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; @@ -260,7 +260,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* If BestFitNode is the first buffer in the list, then update StartOfFreedNodes to reflect the new free node - */ + */ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; } else { @@ -345,10 +345,10 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) FreedNodePtr->NextNodeOffset = 0; } else { - /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the size of BIOS_BUFFER_NODE - */ + */ AllocNodePtr->NextNodeOffset = FreedNodeOffset; } /* Update StartOfFreedNodes to the new first node */ @@ -356,7 +356,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } else { /* Traverse list of freed nodes to find where the deallocated node should be place - */ + */ NextNodeOffset = FreedNodeOffset; NextNodePtr = FreedNodePtr; while (AllocNodeOffset > NextNodeOffset) { @@ -370,7 +370,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* If deallocated node is adjacent to the next node, concatenate both nodes - */ + */ if (NextNodeOffset == EndNodeOffset) { NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); AllocNodePtr->BufferSize += NextNodePtr->BufferSize; @@ -384,7 +384,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* If deallocated node is adjacent to the previous node, concatenate both nodes - */ + */ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; if (AllocNodeOffset == EndNodeOffset) { @@ -448,10 +448,10 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) UINT8 Value; UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader; - + ResetType = Data; StdHeader = ConfigPtr; - + // // Perform the RESET based upon the ResetType. In case of // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to @@ -463,17 +463,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) case WARM_RESET_WHENEVER: case COLD_RESET_WHENEVER: break; - + case WARM_RESET_IMMEDIATELY: case COLD_RESET_IMMEDIATELY: Value = 0x06; LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); break; - + default: break; } - + Status = 0; return Status; } @@ -506,10 +506,10 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) UINT8 Data8; UINT16 Data16; UINT8 TempData8; - + FcnData = Data; MemData = ConfigPtr; - + Status = AGESA_SUCCESS; /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8 (0xCD6, 0x27); @@ -520,14 +520,14 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); Data8 &= ~BIT5; TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); TempData8 &= 0x03; TempData8 |= Data8; Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - + Data8 |= BIT2+BIT3; Data8 &= ~BIT4; TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); @@ -546,7 +546,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) TempData8 &= 0x23; TempData8 |= Data8; Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - + switch(MemData->ParameterListPtr->DDR3Voltage){ case VOLT1_35: Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); @@ -586,12 +586,12 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS Status; UINTN FcnData; PCIe_SLOT_RESET_INFO *ResetInfo; - + UINT32 GpioMmioAddr; UINT32 AcpiMmioAddr; UINT8 Data8; UINT16 Data16; - + FcnData = Data; ResetInfo = ConfigPtr; // Get SB800 MMIO Base (AcpiMmioAddr) @@ -611,13 +611,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; + Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; @@ -634,7 +634,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; + Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/amd/inagua/BiosCallOuts.h b/src/mainboard/amd/inagua/BiosCallOuts.h index 2912ec6f51..4efe15fa4d 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.h +++ b/src/mainboard/amd/inagua/BiosCallOuts.h @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #ifndef _BIOS_CALLOUT_H_ #define _BIOS_CALLOUT_H_ @@ -45,7 +45,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* REQUIRED CALLOUTS * AGESA ADVANCED CALLOUTS - CPU - */ + */ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c index 1840afc552..4f000717fe 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcie.c +++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c @@ -56,7 +56,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) - } + } }; PCIe_DDI_DESCRIPTOR DdiList [] = { @@ -116,8 +116,8 @@ OemCustomizeInitEarly ( // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + sizeof (PCIe_DDI_DESCRIPTOR)) * 2; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; @@ -125,10 +125,10 @@ OemCustomizeInitEarly ( Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); if ( Status!= AGESA_SUCCESS) { // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - ASSERT(FALSE); + ASSERT(FALSE); return Status; } - + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); @@ -136,7 +136,7 @@ OemCustomizeInitEarly ( AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - + LibAmdMemFill (BrazosPcieComplexListPtr, 0, sizeof (PCIe_COMPLEX_DESCRIPTOR), @@ -146,7 +146,7 @@ OemCustomizeInitEarly ( 0, sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - + LibAmdMemFill (BrazosPcieDdiPtr, 0, sizeof (PCIe_DDI_DESCRIPTOR) * 2, @@ -160,7 +160,7 @@ OemCustomizeInitEarly ( ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; - InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; - InitEarly->GnbConfig.PsppPolicy = 0; + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; } diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h index f35d8db723..b51089f7f6 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h @@ -25,42 +25,42 @@ #include "amdlib.h" //GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced @@ -68,5 +68,5 @@ VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ); - + #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 4c084e0aba..cc37ed24b0 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -62,18 +62,18 @@ unsigned long acpi_fill_mcfg(unsigned long current) unsigned long acpi_fill_madt(unsigned long current) { - + /* create all subtables for processors */ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1); - + /* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb800, IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); - + /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c index cbdb23d5ed..df5cd1e9a9 100644 --- a/src/mainboard/amd/inagua/agesawrapper.c +++ b/src/mainboard/amd/inagua/agesawrapper.c @@ -21,7 +21,7 @@ * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */ - + #include <stdint.h> #include <string.h> #include "agesawrapper.h" @@ -52,8 +52,8 @@ VOID *AcpiSlit = NULL; VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; - +VOID *AcpiAlib = NULL; + /*---------------------------------------------------------------------------------------- * T Y P E D E F S A N D S T R U C T U R E S @@ -64,17 +64,17 @@ VOID *AcpiAlib = NULL; * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + /*--------------------------------------------------------------------------------------- * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ -UINT32 +UINT32 agesawrapper_amdinitcpuio ( VOID ) @@ -84,30 +84,30 @@ agesawrapper_amdinitcpuio ( UINT32 PciData; PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; - + /* Enable MMIO on AMD CPU Address Map Controller */ - + /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); PciData = 0x00000B00; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); PciData = 0x00000A03; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - + /* Set TOM-DFFFFFFF to Node0 Link0. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); PciData = 0x00DFFF00; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC); PciData = 0x00FFFF00 | 0x80; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8); PciData = (PCIE_BASE_ADDRESS >> 8) | 03; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); @@ -121,8 +121,8 @@ agesawrapper_amdinitcpuio ( Status = AGESA_SUCCESS; return (UINT32)Status; } - -UINT32 + +UINT32 agesawrapper_amdinitmmio ( VOID ) @@ -132,29 +132,29 @@ agesawrapper_amdinitmmio ( UINT32 PciData; PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; - + /* Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Address MSR register. */ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1; LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - + /* Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. */ LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - + /* Set Ontario Link Data */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); PciData = 0x01308002; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; @@ -166,7 +166,7 @@ agesawrapper_amdinitmmio ( return (UINT32)Status; } -UINT32 +UINT32 agesawrapper_amdinitreset ( VOID ) @@ -174,7 +174,7 @@ agesawrapper_amdinitreset ( AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESET_PARAMS AmdResetParams; - + LibAmdMemFill (&AmdParamStruct, 0, sizeof (AMD_INTERFACE_PARAMS), @@ -196,14 +196,14 @@ agesawrapper_amdinitreset ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; - + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); return (UINT32)status; - } - -UINT32 + } + +UINT32 agesawrapper_amdinitearly ( VOID ) @@ -211,7 +211,7 @@ agesawrapper_amdinitearly ( AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - + LibAmdMemFill (&AmdParamStruct, 0, sizeof (AMD_INTERFACE_PARAMS), @@ -224,10 +224,10 @@ agesawrapper_amdinitearly ( AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); - + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; OemCustomizeInitEarly (AmdEarlyParamsPtr); - + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); @@ -235,7 +235,7 @@ agesawrapper_amdinitearly ( return (UINT32)status; } -UINT32 +UINT32 agesawrapper_amdinitpost ( VOID ) @@ -277,7 +277,7 @@ agesawrapper_amdinitpost ( return (UINT32)status; } -UINT32 +UINT32 agesawrapper_amdinitenv ( VOID ) @@ -304,7 +304,7 @@ agesawrapper_amdinitenv ( /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 - */ + */ PciAddress.Address.Bus = 0; PciAddress.Address.Device = 1; PciAddress.Address.Function = 0; @@ -407,17 +407,17 @@ agesawrapper_getlateinitptr ( } } -UINT32 +UINT32 agesawrapper_amdinitmid ( VOID ) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - + /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio (); - + LibAmdMemFill (&AmdParamStruct, 0, sizeof (AMD_INTERFACE_PARAMS), @@ -439,7 +439,7 @@ agesawrapper_amdinitmid ( return (UINT32)status; } -UINT32 +UINT32 agesawrapper_amdinitlate ( VOID ) @@ -475,9 +475,9 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } -UINT32 +UINT32 agesawrapper_amdlaterunaptask ( - UINT32 Data, + UINT32 Data, VOID *ConfigPtr ) { @@ -512,7 +512,7 @@ agesawrapper_amdlaterunaptask ( return (UINT32)Status; } -UINT32 +UINT32 agesawrapper_amdreadeventlog ( VOID ) diff --git a/src/mainboard/amd/inagua/agesawrapper.h b/src/mainboard/amd/inagua/agesawrapper.h index fd46dc6358..f6e6decad6 100644 --- a/src/mainboard/amd/inagua/agesawrapper.h +++ b/src/mainboard/amd/inagua/agesawrapper.h @@ -21,8 +21,8 @@ * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */ - - + + #ifndef _AGESAWRAPPER_H_ #define _AGESAWRAPPER_H_ @@ -66,17 +66,17 @@ typedef struct { * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + /*--------------------------------------------------------------------------------------- * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ - + //void brazos_platform_stage(void); UINT32 agesawrapper_amdinitreset (void); UINT32 agesawrapper_amdinitearly (void); diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 686f7fa717..919f6be907 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + /** * @file * @@ -57,13 +57,13 @@ #define INSTALL_FT1_SOCKET_SUPPORT TRUE #define INSTALL_AM3_SOCKET_SUPPORT FALSE -/* - * Agesa optional capabilities selection. +/* + * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE #define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE @@ -104,7 +104,7 @@ //#define BLDOPT_REMOVE_HT_ASSIST TRUE //#define BLDOPT_REMOVE_ATM_MODE TRUE //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE //#define BLDOPT_REMOVE_C6_STATE TRUE //#define BLDOPT_REMOVE_GFX_RECOVERY TRUE @@ -125,10 +125,10 @@ #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE -/* - * Agesa configuration values selection. +/* + * Agesa configuration values selection. * Uncomment and specify the value for the configuration options - * needed by the system. + * needed by the system. */ /* The fixed MTRR values to be set after memory initialization. */ diff --git a/src/mainboard/amd/inagua/dimmSpd.c b/src/mainboard/amd/inagua/dimmSpd.c index d6bf5b28e1..d82cb5d2c0 100644 --- a/src/mainboard/amd/inagua/dimmSpd.c +++ b/src/mainboard/amd/inagua/dimmSpd.c @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #include "Porting.h" #include "AGESA.h" #include "amdlib.h" @@ -51,7 +51,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset) UINT64 limit; address |= 1; // set read bit - + __outbyte (iobase + 0, 0xFF); // clear error status __outbyte (iobase + 1, 0x1F); // clear error status __outbyte (iobase + 3, offset); // offset in eeprom @@ -108,7 +108,7 @@ static int readSmbusByte (int iobase, int address, char *buffer) * * readspd - Read one or more SPD bytes from a DIMM. * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid + * Optimization relies on autoincrement to avoid * sending offset for every byte. * Reads 128 bytes in 7-8 ms at 400 KHz. */ @@ -127,7 +127,7 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); if (error) return error; } - + return 0; } @@ -150,11 +150,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA { int spdAddress, ioBase; - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + + spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; if (spdAddress == 0) return AGESA_ERROR; ioBase = SMBUS_BASE_ADDR; setupFch (ioBase); diff --git a/src/mainboard/amd/inagua/dimmSpd.h b/src/mainboard/amd/inagua/dimmSpd.h index 069c34a6fc..069c34a6fc 100755..100644 --- a/src/mainboard/amd/inagua/dimmSpd.h +++ b/src/mainboard/amd/inagua/dimmSpd.h diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c index fedab7531a..ab58c99aea 100644 --- a/src/mainboard/amd/inagua/get_bus_conf.c +++ b/src/mainboard/amd/inagua/get_bus_conf.c @@ -79,22 +79,22 @@ void get_bus_conf(void) * This is the call to AmdInitLate. It is really in the wrong place, conceptually, * but functionally within the coreboot model, this is the best place to make the * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "hardwaremain". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are * called before the ACPI tables are written. This routine is called at the beginning * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ - status = agesawrapper_amdinitlate(); + status = agesawrapper_amdinitlate(); if(status) { printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); } - + sbdn_sb800 = 0; for (i = 0; i < 3; i++) { diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index fa7de7d122..7278936902 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -37,15 +37,15 @@ extern u32 sbdn_sb800; u32 apicid_sb800; u8 picr_data[] = { - 0x0B,0x0A,0x0B,0x05,0x1F,0x1F,0x1F,0x1F,0x50,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x1F,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x0B,0x0A,0x0B,0x05,0x1F,0x1F,0x1F,0x1F,0x50,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x1F,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x0A,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x0B,0x0A,0x0B,0x05 }; u8 intr_data[] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v) 0, apic_version, cpu_flag, cpu_features, cpu_feature_flags ); - + cpu_flag = MPC_CPU_ENABLED; smp_write_processor(mc, 1, apic_version, @@ -112,11 +112,11 @@ static void *smp_write_config_table(void *v) my_smp_write_bus(mc, bus_isa, "ISA "); /* I/O APICs: APIC ID Version State Address */ - + device_t dev; u32 dword; u8 byte; - + ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); dword &= 0xFFFFFFF0; /* Set IO APIC ID onto IO_APIC_ID */ @@ -124,13 +124,13 @@ static void *smp_write_config_table(void *v) write32 (dword + 0x10, IO_APIC_ID << 24); apicid_sb800 = IO_APIC_ID; smp_write_ioapic(mc, apicid_sb800, 0x21, dword); - + /* PIC IRQ routine */ for (byte = 0x0; byte < sizeof(picr_data); byte ++) { outb(byte, 0xC00); outb(picr_data[byte], 0xC01); } - + /* APIC IRQ routine */ for (byte = 0x0; byte < sizeof(intr_data); byte ++) { outb(byte | 0x80, 0xC00); @@ -168,12 +168,12 @@ static void *smp_write_config_table(void *v) /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); - + /* HD Audio */ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); - + /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); @@ -187,7 +187,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ - + /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 3fb0e875db..3cfd741755 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -91,7 +91,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return CalloutStatus; } } - + return CalloutStatus; } @@ -289,7 +289,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } else { /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the + Update NextNodeOffset and BufferSize to include the size of BIOS_BUFFER_NODE */ AllocNodePtr->NextNodeOffset = FreedNodeOffset; @@ -470,7 +470,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) TempData8 &= 0x03; TempData8 |= Data8; Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - + Data8 |= BIT2+BIT3; Data8 &= ~BIT4; TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); @@ -563,13 +563,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; + Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; @@ -586,7 +586,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; + Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index b187fa25c0..b7c78830b4 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #ifndef _BIOS_CALLOUT_H_ #define _BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index 59d31efb77..b0389b82d9 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -86,7 +86,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) - } + } }; PCIe_DDI_DESCRIPTOR DdiList [] = { @@ -118,8 +118,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + sizeof (PCIe_DDI_DESCRIPTOR)) * 2; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; @@ -127,10 +127,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); if ( Status!= AGESA_SUCCESS) { // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - ASSERT(FALSE); + ASSERT(FALSE); return; } - + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); @@ -138,7 +138,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - + LibAmdMemFill (BrazosPcieComplexListPtr, 0, sizeof (PCIe_COMPLEX_DESCRIPTOR), @@ -148,7 +148,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { 0, sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - + LibAmdMemFill (BrazosPcieDdiPtr, 0, sizeof (PCIe_DDI_DESCRIPTOR) * 2, @@ -162,7 +162,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; - InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; - InitEarly->GnbConfig.PsppPolicy = 0; + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; } diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index f35d8db723..b51089f7f6 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -25,42 +25,42 @@ #include "amdlib.h" //GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced @@ -68,5 +68,5 @@ VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ); - + #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 74aa73d49f..9d9f864141 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -86,11 +86,11 @@ agesawrapper_amdinitcpuio ( UINT32 PciData; PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; - + /* Enable legacy video routing: D18F1xF4 VGA Enable */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* The platform BIOS needs to ensure the memory ranges of SB800 legacy * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are @@ -99,21 +99,21 @@ agesawrapper_amdinitcpuio ( PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 PciData |= 1 << 7; // set NP (non-posted) bit - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + /* Map the remaining PCI hole as posted MMIO */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); PciData = 0x00FECF00; // last address before non-posted range - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + /* Send all IO (0000-FFFF) to southbridge. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); PciData = 0x0000F000; @@ -135,7 +135,7 @@ agesawrapper_amdinitmmio ( UINT32 PciData; PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; - + UINT8 BusRangeVal = 0; UINT8 BusNum; UINT8 Index; @@ -166,10 +166,10 @@ agesawrapper_amdinitmmio ( /* Set Ontario Link Data */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); PciData = 0x01308002; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); Status = AGESA_SUCCESS; return (UINT32)Status; @@ -313,7 +313,7 @@ agesawrapper_amdinitenv ( /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 - */ + */ PciAddress.Address.Bus = 0; PciAddress.Address.Device = 1; PciAddress.Address.Function = 0; @@ -480,10 +480,10 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } -UINT32 +UINT32 agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, + UINT32 Func, + UINT32 Data, VOID *ConfigPtr ) { diff --git a/src/mainboard/amd/persimmon/dimmSpd.c b/src/mainboard/amd/persimmon/dimmSpd.c index 9da0e0e3a8..2bd27d6f42 100644 --- a/src/mainboard/amd/persimmon/dimmSpd.c +++ b/src/mainboard/amd/persimmon/dimmSpd.c @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #include "Porting.h" #include "AGESA.h" #include "amdlib.h" @@ -55,7 +55,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset) UINT64 limit; address |= 1; // set read bit - + __outbyte (iobase + 0, 0xFF); // clear error status __outbyte (iobase + 1, 0x1F); // clear error status __outbyte (iobase + 3, offset); // offset in eeprom @@ -112,7 +112,7 @@ static int readSmbusByte (int iobase, int address, char *buffer) * * readspd - Read one or more SPD bytes from a DIMM. * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid + * Optimization relies on autoincrement to avoid * sending offset for every byte. * Reads 128 bytes in 7-8 ms at 400 KHz. */ @@ -131,7 +131,7 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); if (error) return error; } - + return 0; } @@ -154,11 +154,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA { int spdAddress, ioBase; - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + + spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; if (spdAddress == 0) return AGESA_ERROR; ioBase = 0xB00; setupFch (ioBase); diff --git a/src/mainboard/amd/persimmon/dimmSpd.h b/src/mainboard/amd/persimmon/dimmSpd.h index 069c34a6fc..069c34a6fc 100755..100644 --- a/src/mainboard/amd/persimmon/dimmSpd.h +++ b/src/mainboard/amd/persimmon/dimmSpd.h diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 4bc5b48218..2d28023574 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -69,22 +69,22 @@ void get_bus_conf(void) * This is the call to AmdInitLate. It is really in the wrong place, conceptually, * but functionally within the coreboot model, this is the best place to make the * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "hardwaremain". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are * called before the ACPI tables are written. This routine is called at the beginning * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ - status = agesawrapper_amdinitlate(); + status = agesawrapper_amdinitlate(); if(status) { printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); } - + sbdn_sb800 = 0; for (i = 0; i < 3; i++) { diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index a3b4b5c95e..546d9bd393 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -61,10 +61,10 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ - + u32 dword; u8 byte; - + ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); dword &= 0xFFFFFFF0; smp_write_ioapic(mc, apicid_sb800, 0x21, dword); @@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v) /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ /* on board NIC & Slot PCIE. */ - + /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c index 126b464305..65ac2e641c 100644 --- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c @@ -57,7 +57,7 @@ void hardwaremain(int ret_addr) train_ram(id.nodeid, sysinfo, sysinfox); /* - * go back, but can not use stack any more, because we + * go back, but can not use stack any more, because we * only keep ret_addr and can not restore esp, and ebp. */ diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 357bdac230..357bdac230 100755..100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 52cab42eb4..52cab42eb4 100755..100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index 355077f189..355077f189 100755..100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.h b/src/mainboard/amd/torpedo/BiosCallOuts.h index 4be7a04c28..4be7a04c28 100755..100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.h +++ b/src/mainboard/amd/torpedo/BiosCallOuts.h diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h index a7109dc382..a7109dc382 100755..100644 --- a/src/mainboard/amd/torpedo/Oem.h +++ b/src/mainboard/amd/torpedo/Oem.h diff --git a/src/mainboard/amd/torpedo/OptionsIds.h b/src/mainboard/amd/torpedo/OptionsIds.h index e3a1d73add..e3a1d73add 100755..100644 --- a/src/mainboard/amd/torpedo/OptionsIds.h +++ b/src/mainboard/amd/torpedo/OptionsIds.h diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcie.c b/src/mainboard/amd/torpedo/PlatformGnbPcie.c index 2d011d97a4..2d011d97a4 100755..100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcie.c +++ b/src/mainboard/amd/torpedo/PlatformGnbPcie.c diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h index f35d8db723..b51089f7f6 100755..100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h @@ -25,42 +25,42 @@ #include "amdlib.h" //GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced @@ -68,5 +68,5 @@ VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ); - + #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c index 7f4f2d9466..4710b57c2a 100755..100644 --- a/src/mainboard/amd/torpedo/acpi_tables.c +++ b/src/mainboard/amd/torpedo/acpi_tables.c @@ -62,13 +62,13 @@ unsigned long acpi_fill_mcfg(unsigned long current) unsigned long acpi_fill_madt(unsigned long current) { - + /* create all subtables for processors */ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 2); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 3); - + /* Write SB900 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb900, IO_APIC_ADDR, 0); @@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current) current, 0, 0, 2, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0xF); - + /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ diff --git a/src/mainboard/amd/torpedo/agesawrapper.c b/src/mainboard/amd/torpedo/agesawrapper.c index 2995856ec4..2995856ec4 100755..100644 --- a/src/mainboard/amd/torpedo/agesawrapper.c +++ b/src/mainboard/amd/torpedo/agesawrapper.c diff --git a/src/mainboard/amd/torpedo/agesawrapper.h b/src/mainboard/amd/torpedo/agesawrapper.h index c3209f5f49..c3209f5f49 100755..100644 --- a/src/mainboard/amd/torpedo/agesawrapper.h +++ b/src/mainboard/amd/torpedo/agesawrapper.h diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c index 0379a812e4..0379a812e4 100755..100644 --- a/src/mainboard/amd/torpedo/buildOpts.c +++ b/src/mainboard/amd/torpedo/buildOpts.c diff --git a/src/mainboard/amd/torpedo/chip.h b/src/mainboard/amd/torpedo/chip.h index a252705293..a252705293 100755..100644 --- a/src/mainboard/amd/torpedo/chip.h +++ b/src/mainboard/amd/torpedo/chip.h diff --git a/src/mainboard/amd/torpedo/dimmSpd.c b/src/mainboard/amd/torpedo/dimmSpd.c index 55fb2c3b22..55fb2c3b22 100755..100644 --- a/src/mainboard/amd/torpedo/dimmSpd.c +++ b/src/mainboard/amd/torpedo/dimmSpd.c diff --git a/src/mainboard/amd/torpedo/dimmSpd.h b/src/mainboard/amd/torpedo/dimmSpd.h index 069c34a6fc..069c34a6fc 100755..100644 --- a/src/mainboard/amd/torpedo/dimmSpd.h +++ b/src/mainboard/amd/torpedo/dimmSpd.h diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index 5701dabc22..5701dabc22 100755..100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c index f9b4c84eb6..13019ff91f 100755..100644 --- a/src/mainboard/amd/torpedo/get_bus_conf.c +++ b/src/mainboard/amd/torpedo/get_bus_conf.c @@ -79,23 +79,23 @@ void get_bus_conf(void) * This is the call to AmdInitLate. It is really in the wrong place, conceptually, * but functionally within the coreboot model, this is the best place to make the * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "hardwaremain". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are * called before the ACPI tables are written. This routine is called at the beginning * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ - status = agesawrapper_amdinitlate(); + status = agesawrapper_amdinitlate(); if(status) { printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n"); - + sbdn_sb900 = 0; for (i = 0; i < 3; i++) { diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index 14dcd2c57b..2633fb5782 100755..100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -21,7 +21,7 @@ * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */ - + #include "Filecode.h" #include "Hudson-2.h" #include "AmdSbLib.h" @@ -63,12 +63,12 @@ *---------------------------------------------------------------------------------------- */ void gpioEarlyInit (void); - + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + /*--------------------------------------------------------------------------------------- * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- @@ -98,7 +98,7 @@ gpioEarlyInit( Data8 |= BIT0; WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); // Get HUDSON MMIO Base (AcpiMmioAddr) - ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8); + ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8); Data16 = Data8 << 8; ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8); Data16 |= Data8; @@ -113,14 +113,14 @@ gpioEarlyInit( Data8 = Mmio8_G (GpioMmioAddr, GPIO_30); StripInfo = (Data8 & BIT7) >> 7; Data8 = Mmio8_G (GpioMmioAddr, GPIO_31); - StripInfo |= (Data8 & BIT7) >> 6; - if (StripInfo < boardRevC) { // for old board. Rev B + StripInfo |= (Data8 & BIT7) >> 6; + if (StripInfo < boardRevC) { // for old board. Rev B Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3 - Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 + Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 } for (Index = 0; Index < MAX_GPIO_NO; Index++) { if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) { - if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) { + if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) { // Configure multi-funtion Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); } @@ -138,7 +138,7 @@ gpioEarlyInit( // Configure GEVENT if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) { SmiMmioAddr = AcpiMmioAddr + SMI_BASE; - + andMask32 = ~(1 << (Index - GEVENT_00)); //EventEnable: 0-Disable, 1-Enable @@ -159,12 +159,12 @@ gpioEarlyInit( //SciMap: 00000b ~ 11111b RegIndex8=(u8)((Index - GEVENT_00) >> 2); Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8); - Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8)); - + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8)); + //SmiTrig: 0-Active Low, 1-Active High Mmio32_And_Or (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00))); - - //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 + + //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 RegIndex8=(u8)((Index - GEVENT_00) >> 4); Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2); Mmio32_And_Or (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8)); @@ -180,7 +180,7 @@ gpioEarlyInit( // GPIO45: Output for MXM Power Enable, active HIGH // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO - // + // // set INTE#/GPIO32 as GPO for PCIE_SW RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO @@ -224,7 +224,7 @@ gpioEarlyInit( //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20)); //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20))); - // check if there any GFX card + // check if there any GFX card Flags = 0; // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL); // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09); @@ -244,13 +244,13 @@ gpioEarlyInit( RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0); // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6); - - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6); + + //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) SbStall (10000); // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module - RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6); + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6); //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) // WAIT POWER READY: GPIO28 (MXM_PWRGD) @@ -261,7 +261,7 @@ gpioEarlyInit( ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); } // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset - // RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); + // RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); } else { @@ -270,9 +270,9 @@ gpioEarlyInit( //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) SbStall (10000); - + // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down - RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0); } // @@ -288,7 +288,7 @@ gpioEarlyInit( RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: + // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH @@ -298,7 +298,7 @@ gpioEarlyInit( // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3 - + // // APU GPP1: WUSB // GPIO1: MPCIE_RST2#, LOW active @@ -354,7 +354,7 @@ gpioEarlyInit( // GPIO41: CLKREQ# // Clock: GPP_CLK8 // - // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: + // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH @@ -382,8 +382,8 @@ gpioEarlyInit( if (!CONFIG_ONBOARD_LAN) { // 1 - DISABLED RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3 } // else @@ -409,11 +409,11 @@ gpioEarlyInit( // else // { // 0 - AUTO // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH) -// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); +// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); -// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); +// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // } // @@ -430,7 +430,7 @@ gpioEarlyInit( RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7 + RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7 RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE } // } @@ -447,25 +447,25 @@ if (!CONFIG_ONBOARD_BLUETOOTH) { } // -// WebCam control: +// WebCam control: // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF // if (!CONFIG_ONBOARD_WEBCAM) { //- if (SystemConfiguration.amdWebCam == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); -//- } +//- } } // -// Travis enable: +// Travis enable: // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE // if (!CONFIG_ONBOARD_TRAVIS) { //- if (SystemConfiguration.amdTravisCtrl == 0) { RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); -//- } +//- } } // diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h index 159394e292..45394efe1d 100755..100644 --- a/src/mainboard/amd/torpedo/gpio.h +++ b/src/mainboard/amd/torpedo/gpio.h @@ -21,8 +21,8 @@ * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */ - - + + #ifndef _GPIO_H_ #define _GPIO_H_ @@ -121,8 +121,8 @@ #define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED #define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. #define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) -#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) -#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE +#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) +#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE // 1:BATTERY IS FINE(DEFAULT) // 0:BATTERY IS LOW #define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF @@ -143,7 +143,7 @@ // 0:USB3.0 I/F in Express CARD // 1:PCIE I/F in Express CARD detection #define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF -#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# +#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# #define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC #define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED #define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED @@ -152,7 +152,7 @@ #define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# #define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# #define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK -#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE +#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE #define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF #define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# #define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA @@ -215,7 +215,7 @@ #define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active #define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, // there is a confliction to IR function when this pin is as a GEVENT. -#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, +#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, // special pin difination for SB900 VGA OUTPUT, high active, // VGA power for Hudson-M2 will be down when it was asserted. #define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active @@ -223,7 +223,7 @@ #define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 #define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 #define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active - // [option for SPI_TPM_CS# in Hudson-M2 A12)] + // [option for SPI_TPM_CS# in Hudson-M2 A12)] #define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & // USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time #define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, @@ -238,7 +238,7 @@ #define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# #define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT #define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 -#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# +#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# #define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI #define GPIO_120_SELECT FUNCTION0+NonGpio #define GPIO_121_SELECT FUNCTION0+NonGpio @@ -287,7 +287,7 @@ #define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM #define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM #define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM #define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 #define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 #define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 @@ -357,18 +357,18 @@ #define TYPE_GPI (1<<5) #define TYPE_GPO (0<<5) - -#define GPIO_00_TYPE TYPE_GPO + +#define GPIO_00_TYPE TYPE_GPO #define GPIO_01_TYPE TYPE_GPO #define GPIO_02_TYPE TYPE_GPO #define GPIO_03_TYPE TYPE_GPO #define GPIO_04_TYPE TYPE_GPO -#define GPIO_05_TYPE TYPE_GPO +#define GPIO_05_TYPE TYPE_GPO #define GPIO_06_TYPE TYPE_GPO #define GPIO_07_TYPE TYPE_GPO #define GPIO_08_TYPE TYPE_GPO #define GPIO_09_TYPE TYPE_GPI -#define GPIO_10_TYPE TYPE_GPI +#define GPIO_10_TYPE TYPE_GPI #define GPIO_11_TYPE TYPE_GPO #define GPIO_12_TYPE TYPE_GPO #define GPIO_13_TYPE TYPE_GPO @@ -397,33 +397,33 @@ #define GPIO_36_TYPE TYPE_GPO #define GPIO_37_TYPE TYPE_GPO #define GPIO_38_TYPE TYPE_GPO -#define GPIO_39_TYPE TYPE_GPO +#define GPIO_39_TYPE TYPE_GPO #define GPIO_40_TYPE TYPE_GPO -#define GPIO_41_TYPE TYPE_GPI +#define GPIO_41_TYPE TYPE_GPI #define GPIO_42_TYPE TYPE_GPI #define GPIO_43_TYPE TYPE_GPO #define GPIO_44_TYPE TYPE_GPO #define GPIO_45_TYPE TYPE_GPO #define GPIO_46_TYPE TYPE_GPI #define GPIO_47_TYPE TYPE_GPO -#define GPIO_48_TYPE TYPE_GPO -#define GPIO_49_TYPE TYPE_GPO +#define GPIO_48_TYPE TYPE_GPO +#define GPIO_49_TYPE TYPE_GPO #define GPIO_50_TYPE TYPE_GPO #define GPIO_51_TYPE TYPE_GPO #define GPIO_52_TYPE TYPE_GPO -#define GPIO_53_TYPE TYPE_GPO -#define GPIO_54_TYPE TYPE_GPO -#define GPIO_55_TYPE TYPE_GPO +#define GPIO_53_TYPE TYPE_GPO +#define GPIO_54_TYPE TYPE_GPO +#define GPIO_55_TYPE TYPE_GPO #define GPIO_56_TYPE TYPE_GPI #define GPIO_57_TYPE TYPE_GPO -#define GPIO_58_TYPE TYPE_GPO +#define GPIO_58_TYPE TYPE_GPO #define GPIO_59_TYPE TYPE_GPO #define GPIO_60_TYPE TYPE_GPI #define GPIO_61_TYPE TYPE_GPI #define GPIO_62_TYPE TYPE_GPI #define GPIO_63_TYPE TYPE_GPI #define GPIO_64_TYPE TYPE_GPI -#define GPIO_65_TYPE TYPE_GPI +#define GPIO_65_TYPE TYPE_GPI #define GPIO_66_TYPE TYPE_GPO #define GPIO_67_TYPE TYPE_GPO #define GPIO_68_TYPE TYPE_GPO @@ -460,17 +460,17 @@ #define GPIO_97_TYPE TYPE_GPI #define GPIO_98_TYPE TYPE_GPI #define GPIO_99_TYPE TYPE_GPI -#define GPIO_100_TYPE TYPE_GPI +#define GPIO_100_TYPE TYPE_GPI #define GPIO_101_TYPE TYPE_GPI #define GPIO_102_TYPE TYPE_GPO #define GPIO_103_TYPE TYPE_GPO #define GPIO_104_TYPE TYPE_GPI -#define GPIO_105_TYPE TYPE_GPI +#define GPIO_105_TYPE TYPE_GPI #define GPIO_106_TYPE TYPE_GPO #define GPIO_107_TYPE TYPE_GPI #define GPIO_108_TYPE TYPE_GPI #define GPIO_109_TYPE TYPE_GPI -#define GPIO_110_TYPE TYPE_GPI +#define GPIO_110_TYPE TYPE_GPI #define GPIO_111_TYPE TYPE_GPI #define GPIO_112_TYPE TYPE_GPI #define GPIO_113_TYPE TYPE_GPI @@ -500,33 +500,33 @@ #define GPIO_136_TYPE TYPE_GPO #define GPIO_137_TYPE TYPE_GPO #define GPIO_138_TYPE TYPE_GPO -#define GPIO_139_TYPE TYPE_GPO +#define GPIO_139_TYPE TYPE_GPO #define GPIO_140_TYPE TYPE_GPO -#define GPIO_141_TYPE TYPE_GPO +#define GPIO_141_TYPE TYPE_GPO #define GPIO_142_TYPE TYPE_GPO #define GPIO_143_TYPE TYPE_GPO #define GPIO_144_TYPE TYPE_GPO #define GPIO_145_TYPE TYPE_GPO #define GPIO_146_TYPE TYPE_GPO #define GPIO_147_TYPE TYPE_GPO -#define GPIO_148_TYPE TYPE_GPO -#define GPIO_149_TYPE TYPE_GPO +#define GPIO_148_TYPE TYPE_GPO +#define GPIO_149_TYPE TYPE_GPO #define GPIO_150_TYPE TYPE_GPO #define GPIO_151_TYPE TYPE_GPO #define GPIO_152_TYPE TYPE_GPO -#define GPIO_153_TYPE TYPE_GPO -#define GPIO_154_TYPE TYPE_GPO -#define GPIO_155_TYPE TYPE_GPO +#define GPIO_153_TYPE TYPE_GPO +#define GPIO_154_TYPE TYPE_GPO +#define GPIO_155_TYPE TYPE_GPO #define GPIO_156_TYPE TYPE_GPO #define GPIO_157_TYPE TYPE_GPO -#define GPIO_158_TYPE TYPE_GPO +#define GPIO_158_TYPE TYPE_GPO #define GPIO_159_TYPE TYPE_GPO #define GPIO_160_TYPE TYPE_GPO #define GPIO_161_TYPE TYPE_GPO #define GPIO_162_TYPE TYPE_GPO #define GPIO_163_TYPE TYPE_GPO #define GPIO_164_TYPE TYPE_GPI -#define GPIO_165_TYPE TYPE_GPO +#define GPIO_165_TYPE TYPE_GPO #define GPIO_166_TYPE TYPE_GPI #define GPIO_167_TYPE TYPE_GPI #define GPIO_168_TYPE TYPE_GPI @@ -561,17 +561,17 @@ #define GPIO_197_TYPE TYPE_GPO #define GPIO_198_TYPE TYPE_GPO #define GPIO_199_TYPE TYPE_GPI -#define GPIO_200_TYPE TYPE_GPO +#define GPIO_200_TYPE TYPE_GPO #define GPIO_201_TYPE TYPE_GPI #define GPIO_202_TYPE TYPE_GPI #define GPIO_203_TYPE TYPE_GPI #define GPIO_204_TYPE TYPE_GPI -#define GPIO_205_TYPE TYPE_GPI +#define GPIO_205_TYPE TYPE_GPI #define GPIO_206_TYPE TYPE_GPI #define GPIO_207_TYPE TYPE_GPI #define GPIO_208_TYPE TYPE_GPI #define GPIO_209_TYPE TYPE_GPO -#define GPIO_210_TYPE TYPE_GPO +#define GPIO_210_TYPE TYPE_GPO #define GPIO_211_TYPE TYPE_GPO #define GPIO_212_TYPE TYPE_GPO #define GPIO_213_TYPE TYPE_GPO @@ -595,17 +595,17 @@ #define GPO_LOW (0<<6) #define GPO_HI (1<<6) -#define GPO_00_LEVEL GPO_HI +#define GPO_00_LEVEL GPO_HI #define GPO_01_LEVEL GPO_HI #define GPO_02_LEVEL GPO_HI #define GPO_03_LEVEL GPO_HI #define GPO_04_LEVEL GPO_HI -#define GPO_05_LEVEL GPO_HI +#define GPO_05_LEVEL GPO_HI #define GPO_06_LEVEL GPO_HI #define GPO_07_LEVEL GPO_HI #define GPO_08_LEVEL GPO_HI #define GPO_09_LEVEL GPO_LOW -#define GPO_10_LEVEL GPO_LOW +#define GPO_10_LEVEL GPO_LOW #define GPO_11_LEVEL GPO_HI #define GPO_12_LEVEL GPO_HI #define GPO_13_LEVEL GPO_HI @@ -634,16 +634,16 @@ #define GPO_36_LEVEL GPO_LOW #define GPO_37_LEVEL GPO_HI #define GPO_38_LEVEL GPO_HI -#define GPO_39_LEVEL GPO_HI +#define GPO_39_LEVEL GPO_HI #define GPO_40_LEVEL GPO_LOW -#define GPO_41_LEVEL GPO_LOW +#define GPO_41_LEVEL GPO_LOW #define GPO_42_LEVEL GPO_LOW #define GPO_43_LEVEL GPO_LOW #define GPO_44_LEVEL GPO_HI #define GPO_45_LEVEL GPO_HI #define GPO_46_LEVEL GPO_LOW #define GPO_47_LEVEL GPO_LOW -#define GPO_48_LEVEL GPO_LOW +#define GPO_48_LEVEL GPO_LOW #define GPO_49_LEVEL GPO_HI #define GPO_50_LEVEL GPO_HI #define GPO_51_LEVEL GPO_LOW @@ -667,7 +667,7 @@ #define GPO_69_LEVEL GPO_LOW #define GPO_70_LEVEL GPO_LOW #define GPO_71_LEVEL GPO_LOW -#define GPO_72_LEVEL GPO_LOW +#define GPO_72_LEVEL GPO_LOW #define GPO_73_LEVEL GPO_LOW #define GPO_74_LEVEL GPO_LOW #define GPO_75_LEVEL GPO_LOW @@ -695,17 +695,17 @@ #define GPO_97_LEVEL GPO_LOW #define GPO_98_LEVEL GPO_LOW #define GPO_99_LEVEL GPO_LOW -#define GPO_100_LEVEL GPO_LOW +#define GPO_100_LEVEL GPO_LOW #define GPO_101_LEVEL GPO_LOW #define GPO_102_LEVEL GPO_LOW #define GPO_103_LEVEL GPO_LOW #define GPO_104_LEVEL GPO_LOW -#define GPO_105_LEVEL GPO_LOW +#define GPO_105_LEVEL GPO_LOW #define GPO_106_LEVEL GPO_LOW #define GPO_107_LEVEL GPO_LOW #define GPO_108_LEVEL GPO_HI #define GPO_109_LEVEL GPO_LOW -#define GPO_110_LEVEL GPO_HI +#define GPO_110_LEVEL GPO_HI #define GPO_111_LEVEL GPO_HI #define GPO_112_LEVEL GPO_HI #define GPO_113_LEVEL GPO_LOW @@ -734,16 +734,16 @@ #define GPO_136_LEVEL GPO_LOW #define GPO_137_LEVEL GPO_LOW #define GPO_138_LEVEL GPO_LOW -#define GPO_139_LEVEL GPO_LOW +#define GPO_139_LEVEL GPO_LOW #define GPO_140_LEVEL GPO_LOW -#define GPO_141_LEVEL GPO_LOW +#define GPO_141_LEVEL GPO_LOW #define GPO_142_LEVEL GPO_LOW #define GPO_143_LEVEL GPO_LOW #define GPO_144_LEVEL GPO_LOW #define GPO_145_LEVEL GPO_LOW #define GPO_146_LEVEL GPO_LOW #define GPO_147_LEVEL GPO_LOW -#define GPO_148_LEVEL GPO_LOW +#define GPO_148_LEVEL GPO_LOW #define GPO_149_LEVEL GPO_LOW #define GPO_150_LEVEL GPO_LOW #define GPO_151_LEVEL GPO_LOW @@ -795,17 +795,17 @@ #define GPO_197_LEVEL GPO_LOW #define GPO_198_LEVEL GPO_LOW #define GPO_199_LEVEL GPO_LOW -#define GPO_200_LEVEL GPO_HI +#define GPO_200_LEVEL GPO_HI #define GPO_201_LEVEL GPO_LOW #define GPO_202_LEVEL GPO_LOW #define GPO_203_LEVEL GPO_LOW #define GPO_204_LEVEL GPO_LOW -#define GPO_205_LEVEL GPO_LOW +#define GPO_205_LEVEL GPO_LOW #define GPO_206_LEVEL GPO_LOW #define GPO_207_LEVEL GPO_LOW #define GPO_208_LEVEL GPO_LOW #define GPO_209_LEVEL GPO_LOW -#define GPO_210_LEVEL GPO_LOW +#define GPO_210_LEVEL GPO_LOW #define GPO_211_LEVEL GPO_LOW #define GPO_212_LEVEL GPO_LOW #define GPO_213_LEVEL GPO_LOW @@ -2278,9 +2278,9 @@ typedef struct _GEVENT_SETTINGS u8 SciLevl; // 0: Edge trigger, 1: Level Trigger u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI u8 SciS0En; // 0: Disable, 1: Enable - u8 SciMap; // 0000b->1111b + u8 SciMap; // 0000b->1111b u8 SmiTrig; // 0: Active Low, 1: Active High - u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 + u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 } GEVENT_SETTINGS; GEVENT_SETTINGS gevent_table[] = @@ -2315,15 +2315,15 @@ GEVENT_SETTINGS gevent_table[] = * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + /*--------------------------------------------------------------------------------------- * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ - + #endif diff --git a/src/mainboard/amd/torpedo/irq_tables.c b/src/mainboard/amd/torpedo/irq_tables.c index f61f1e896b..f61f1e896b 100755..100644 --- a/src/mainboard/amd/torpedo/irq_tables.c +++ b/src/mainboard/amd/torpedo/irq_tables.c diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 288798fdb2..288798fdb2 100755..100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 03812060c8..2e171a1372 100755..100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -37,15 +37,15 @@ extern u32 sbdn_sb900; u32 apicid_sb900; u8 picr_data[] = { - 0x0B,0x0B,0x0B,0x0B,0x1F,0x1F,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x0B,0x0B,0x0B,0x0B,0x1F,0x1F,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x0B,0x0B,0x0B,0x0B }; u8 intr_data[] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v) 0, apic_version, cpu_flag, cpu_features, cpu_feature_flags ); - + cpu_flag = MPC_CPU_ENABLED; smp_write_processor(mc, 1, apic_version, @@ -112,11 +112,11 @@ static void *smp_write_config_table(void *v) my_smp_write_bus(mc, bus_isa, "ISA "); /* I/O APICs: APIC ID Version State Address */ - + device_t dev; u32 dword; u8 byte; - + dword = 0; dword = pm_ioread(0x34) & 0xF0; dword |= (pm_ioread(0x35) & 0xFF) << 8; @@ -127,13 +127,13 @@ static void *smp_write_config_table(void *v) write32 (dword + 0x10, IO_APIC_ID << 24); apicid_sb900 = IO_APIC_ID; smp_write_ioapic(mc, apicid_sb900, 0x21, dword); - + /* PIC IRQ routine */ for (byte = 0x0; byte < sizeof(picr_data); byte ++) { outb(byte, 0xC00); outb(picr_data[byte], 0xC01); } - + /* APIC IRQ routine */ for (byte = 0x0; byte < sizeof(intr_data); byte ++) { outb(byte | 0x80, 0xC00); @@ -172,15 +172,15 @@ static void *smp_write_config_table(void *v) /* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - + /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); - + /* HD Audio */ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); - + /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); @@ -194,7 +194,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ - + /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sb900[1], 0x5, 0x0, 0x14); diff --git a/src/mainboard/amd/torpedo/pmio.c b/src/mainboard/amd/torpedo/pmio.c index baded54ba6..baded54ba6 100755..100644 --- a/src/mainboard/amd/torpedo/pmio.c +++ b/src/mainboard/amd/torpedo/pmio.c diff --git a/src/mainboard/amd/torpedo/pmio.h b/src/mainboard/amd/torpedo/pmio.h index 207fdc24ab..207fdc24ab 100755..100644 --- a/src/mainboard/amd/torpedo/pmio.h +++ b/src/mainboard/amd/torpedo/pmio.h diff --git a/src/mainboard/amd/torpedo/reset.c b/src/mainboard/amd/torpedo/reset.c index 36bc6e0f17..36bc6e0f17 100755..100644 --- a/src/mainboard/amd/torpedo/reset.c +++ b/src/mainboard/amd/torpedo/reset.c diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 317f697fea..317f697fea 100755..100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c |