diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2009-02-28 20:10:20 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2009-02-28 20:10:20 +0000 |
| commit | 2b34db8d1de2d63ffa829fe03db0ce2aaba40233 (patch) | |
| tree | ba18eb28d25a5e5d28c3b8609b5a292982eed08c /src/mainboard/amd | |
| parent | 3c924d2f48ba1bb6a9d5a20453f230bb6be726e0 (diff) | |
coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/dbm690t/mainboard.c | 14 | ||||
| -rw-r--r-- | src/mainboard/amd/pistachio/mainboard.c | 16 |
2 files changed, 15 insertions, 15 deletions
diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c index ce206b951e..b60fb80b0c 100644 --- a/src/mainboard/amd/dbm690t/mainboard.c +++ b/src/mainboard/amd/dbm690t/mainboard.c @@ -105,24 +105,24 @@ static void get_ide_dma66() byte = pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0xA9); + sm_dev->path.pci.devfn, 0xA9); byte |= (1 << 5); /* Set Gpio9 as input */ pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0xA9, byte); + sm_dev->path.pci.devfn, 0xA9, byte); ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); byte = pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary, - ide_dev->path.u.pci.devfn, 0x56); + ide_dev->path.pci.devfn, 0x56); byte &= ~(7 << 0); if ((1 << 5) & pci_cf8_conf1. - read8(&pbus, sm_dev->bus->secondary, sm_dev->path.u.pci.devfn, + read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xAA)) byte |= 2 << 0; /* mode 2 */ else byte |= 5 << 0; /* mode 5 */ pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary, - ide_dev->path.u.pci.devfn, 0x56, byte); + ide_dev->path.pci.devfn, 0x56, byte); } /* @@ -158,10 +158,10 @@ static void set_thermal_config() sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); word = pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x56); + sm_dev->path.pci.devfn, 0x56); word |= 1 << 7; pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x56, word); + sm_dev->path.pci.devfn, 0x56, word); /* set GPIO 64 internal pull-up */ byte = pm2_ioread(0xf0); diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c index 960c74954d..7651180127 100644 --- a/src/mainboard/amd/pistachio/mainboard.c +++ b/src/mainboard/amd/pistachio/mainboard.c @@ -169,26 +169,26 @@ static void set_thermal_config() sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x64); + sm_dev->path.pci.devfn, 0x64); dword |= 1 << 19; pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x64, dword); + sm_dev->path.pci.devfn, 0x64, dword); /* Enable Client Management Index/Data registers */ dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x78); + sm_dev->path.pci.devfn, 0x78); dword |= 1 << 11; /* Cms_enable */ pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x78, dword); + sm_dev->path.pci.devfn, 0x78, dword); /* MiscfuncEnable */ byte = pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x41); + sm_dev->path.pci.devfn, 0x41); byte |= (1 << 5); pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x41, byte); + sm_dev->path.pci.devfn, 0x41, byte); /* set GPM5 as input */ /* set index register 0C50h to 13h (miscellaneous control) */ @@ -230,10 +230,10 @@ static void set_thermal_config() /* set GPIO 64 to input */ word = pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x56); + sm_dev->path.pci.devfn, 0x56); word |= 1 << 7; pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x56, word); + sm_dev->path.pci.devfn, 0x56, word); /* set GPIO 64 internal pull-up */ byte = pm2_ioread(0xf0); |