diff options
| author | Martin Roth <martinroth@google.com> | 2015-12-10 08:19:27 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-12-16 00:56:08 +0100 |
| commit | 1e1c7ac3b4cb6d85eb602e04b0e4da8c042846c0 (patch) | |
| tree | bc65f4d19be2551d4fdc1456518891ce164963fc /src/mainboard/amd | |
| parent | 49bbfcd5d393b8c14b46e46f0b20f150e4930b3d (diff) | |
southbridge/amd/sb600: Update HPET base address with #define
The SB600 code had the base address of the HPET hardcoded throughout.
It looks like the plan was to have it be updated in ACPI if needed,
but this wasn't ever implemented. The variable names being used to
do this update were the same, causing an IASL warning. Because of
this, the operation to update the HPET address actually did nothing.
This was fine, because it didn't actually need to be updated.
- Replace all that code with a #define.
- Add and update some comments in the same area.
Fixes IASL warning:
dsdt.aml 1505: Store(HPBA, HPBA)
Warning 3023 - ^ Duplicate value in list (Source is the
same as Target)
Change-Id: I9ba5fe226a4a464e0045ce7d3406898760df5e5a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12705
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/dbm690t/dsdt.asl | 13 | ||||
| -rw-r--r-- | src/mainboard/amd/pistachio/dsdt.asl | 13 |
2 files changed, 12 insertions, 14 deletions
diff --git a/src/mainboard/amd/dbm690t/dsdt.asl b/src/mainboard/amd/dbm690t/dsdt.asl index 46d3671576..744c687e35 100644 --- a/src/mainboard/amd/dbm690t/dsdt.asl +++ b/src/mainboard/amd/dbm690t/dsdt.asl @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <southbridge/amd/sb600/sb600.h> + /* DefinitionBlock Statement */ DefinitionBlock ( "DSDT.AML", /* Output filename */ @@ -33,7 +35,6 @@ DefinitionBlock ( Name(PBLN, 0x0) /* Length of BIOS area */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ @@ -1361,20 +1362,18 @@ DefinitionBlock ( }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - Device(HPTM) { + Device(HPTM) { /* HPET */ Name(_HID,EISAID("PNP0103")) Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ + Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */ }) Method(_STA, 0) { - Return(0x0F) /* sata is visible */ + Return(0x0F) /* HPET is visible */ } Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBA) - Store(HPBA, HPBA) Return(CRS) } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */ } /* end LIBR */ Device(HPBR) { diff --git a/src/mainboard/amd/pistachio/dsdt.asl b/src/mainboard/amd/pistachio/dsdt.asl index 6322289c07..0e8bd05789 100644 --- a/src/mainboard/amd/pistachio/dsdt.asl +++ b/src/mainboard/amd/pistachio/dsdt.asl @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <southbridge/amd/sb600/sb600.h> + /* DefinitionBlock Statement */ DefinitionBlock ( "DSDT.AML", /* Output filename */ @@ -33,7 +35,6 @@ DefinitionBlock ( Name(PBLN, 0x0) /* Length of BIOS area */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ @@ -1360,20 +1361,18 @@ DefinitionBlock ( }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - Device(HPTM) { + Device(HPTM) { /* HPET */ Name(_HID,EISAID("PNP0103")) Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ + Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */ }) Method(_STA, 0) { - Return(0x0F) /* sata is visible */ + Return(0x0F) /* HPET is visible */ } Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBA) - Store(HPBA, HPBA) Return(CRS) } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */ } /* end LIBR */ Device(HPBR) { |