diff options
author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-05-06 23:53:09 +1000 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-13 10:03:38 +0200 |
commit | e61dd0f7a2be83ce5ba87d74f7384111576ffd49 (patch) | |
tree | a9f2c51500bbd8702cf039c8e620653d25c4b4d8 /src/mainboard/amd | |
parent | 216a619a74d61f66e3d3e1d668028d11a8868b4d (diff) |
southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge
We should configure i8254/i8259 down in to the southbridge rather than
romstage of every AGESA/CIMx board much like Intel boards do.
Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5669
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r-- | src/mainboard/amd/dinar/romstage.c | 10 | ||||
-rw-r--r-- | src/mainboard/amd/inagua/romstage.c | 10 | ||||
-rw-r--r-- | src/mainboard/amd/olivehill/romstage.c | 9 | ||||
-rw-r--r-- | src/mainboard/amd/parmer/romstage.c | 10 | ||||
-rw-r--r-- | src/mainboard/amd/persimmon/romstage.c | 10 | ||||
-rw-r--r-- | src/mainboard/amd/thatcher/romstage.c | 10 | ||||
-rw-r--r-- | src/mainboard/amd/torpedo/romstage.c | 13 |
7 files changed, 0 insertions, 72 deletions
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 776ecd5e2e..8ed1398521 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -32,8 +32,6 @@ #include "superio/smsc/sch4037/sch4037_early_init.c" #include "superio/smsc/sio1036/sio1036_early_init.c" #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include "nb_cimx.h" #include <sb_cimx.h> #include "Platform.h" @@ -140,14 +138,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x43); print_debug("Disabling cache as ram "); disable_cache_as_ram(); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 98c74d6d03..a304d318b0 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -35,8 +35,6 @@ #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -112,14 +110,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259(); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254(); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 6422393f6a..73cd40a52f 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -34,8 +34,6 @@ #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "cbmem.h" @@ -160,13 +158,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index a5d041fc80..668dfc86dc 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -34,8 +34,6 @@ #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "cbmem.h" @@ -141,14 +139,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 47c03ec54a..9ba34e70af 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -35,8 +35,6 @@ #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -170,14 +168,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 9c3cf5bf64..1a7a399944 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -35,8 +35,6 @@ #include "southbridge/amd/agesa/hudson/hudson.h" #include "src/superio/smsc/lpc47n217/early_serial.c" #include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "cbmem.h" #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) @@ -158,14 +156,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 58b88d0f61..dcab52b647 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -32,8 +32,6 @@ #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include "sb_cimx.h" #include "SbPlatform.h" #include <arch/cpu.h> @@ -112,17 +110,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - /* Initialize i8259 pic */ - post_code(0x41); - printk(BIOS_DEBUG, "setup_i8259\n"); - setup_i8259(); - - /* Initialize i8254 timers */ - post_code(0x42); - printk(BIOS_DEBUG, "setup_i8254\n"); - setup_i8254(); - - post_code(0x43); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run returned!\n"); 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