- Update abuild.sh so it will rebuild successfull builds

- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
  enabled.  All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

12 files changed, 121 insertions, 126 deletions

diff --git a/src/mainboard/amd/quartet/Config.lb b/src/mainboard/amd/quartet/Config.lb
index c9a1d4203e..9b003978b5 100644
--- a/src/mainboard/amd/quartet/Config.lb
+++ b/src/mainboard/amd/quartet/Config.lb
@@ -46,22 +46,22 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c" 
-	action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+	depends "$(MAINBOARD)/failover.c ./romcc" 
+	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "./failover.E ./romcc"
-	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+	depends "$(MAINBOARD)/failover.c ./romcc"
+	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h"
-	action	"$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
+	action	"./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "./auto.E ./romcc"
-	action	"./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##
diff --git a/src/mainboard/amd/quartet/auto.c b/src/mainboard/amd/quartet/auto.c
index 67bc959496..6a3b2194e7 100644
--- a/src/mainboard/amd/quartet/auto.c
+++ b/src/mainboard/amd/quartet/auto.c
@@ -7,7 +7,8 @@
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -16,13 +17,15 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/cpu_rev.c"
 #include "superio/NSC/pc87360/pc87360_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
 
@@ -41,7 +44,10 @@ static void soft_reset(void)
 	pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
 }
 
-
+/*
+ * GPIO28 of 8111 will control H0_MEMRESET_L
+ * GPIO29 of 8111 will control H1_MEMRESET_L
+ */
 static void memreset_setup(void)
 {
 	if (is_cpu_pre_c0()) {
@@ -144,13 +150,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "fakespd.c"
 #endif
 
-#include "northbridge/amd/amdk8/setup_resource_map.c"
+// #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "northbridge/amd/amdk8/raminit.c"
-
 #include "northbridge/amd/amdk8/coherent_ht.c"
-
 #include "sdram/generic_sdram.c"
-
 #include "resourcemap.c"	/* quartet does not want the default */
 
 #define RC0 ((1<<1)<<8)
@@ -163,7 +166,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define DIMM2 0x52
 #define DIMM3 0x53
 
-static void main(void)
+static void main(unsigned long bist)
 {
 	static const struct mem_controller cpu[] = {
 		{
@@ -215,22 +218,30 @@ static void main(void)
 
 	int needs_reset;
 
-	enable_lapic();
-	init_timer();
+	if (bist == 0) {
+		/* Skip this if there was a built in self test failure */
+		amd_early_mtrr_init();
+		enable_lapic();
+		init_timer();
+		/* Has this cpu already booted? */
+		if (cpu_init_detected()) {
+			asm volatile ("jmp __cpu_reset");
+		}
 
-	if (cpu_init_detected()) {
-		asm("jmp __cpu_reset");
-	}
-
-	distinguish_cpu_resets();
+		distinguish_cpu_resets();
 
-	if (!boot_cpu()) {
-		stop_this_cpu();
+		if (!boot_cpu()) {
+			stop_this_cpu();
+		}
 	}
-
+	/* Setup the console */
 	pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
 	uart_init();
 	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
 	setup_quartet_resource_map();
 	needs_reset = setup_coherent_ht_domain();
 //	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
diff --git a/src/mainboard/amd/quartet/chip.h b/src/mainboard/amd/quartet/chip.h
index 526dcc4515..59c2edff48 100644
--- a/src/mainboard/amd/quartet/chip.h
+++ b/src/mainboard/amd/quartet/chip.h
@@ -1,4 +1,4 @@
-extern struct chip_operations mainboard_amd_quartet_control;
+extern struct chip_operations mainboard_amd_quartet_ops;
 
 struct mainboard_amd_quartet_config {
 	int nothing;
diff --git a/src/mainboard/amd/quartet/mainboard.c b/src/mainboard/amd/quartet/mainboard.c
index 4071c3b93d..e72ff2c43a 100644
--- a/src/mainboard/amd/quartet/mainboard.c
+++ b/src/mainboard/amd/quartet/mainboard.c
@@ -3,12 +3,9 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-
-#include <arch/io.h>
-#include "../../../northbridge/amd/amdk8/northbridge.h"
 #include "chip.h"
 
 
-struct chip_operations mainboard_amd_quartet_control = {
-	.name      = "AMD Quartet mainboard ",
+struct chip_operations mainboard_amd_quartet_ops = {
+	CHIP_NAME("AMD Quartet mainboard ")
 };
diff --git a/src/mainboard/amd/quartet/mptable.c b/src/mainboard/amd/quartet/mptable.c
index 03ff598877..9d3ea13127 100644
--- a/src/mainboard/amd/quartet/mptable.c
+++ b/src/mainboard/amd/quartet/mptable.c
@@ -4,7 +4,7 @@
 #include <string.h>
 #include <stdint.h>
 
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
 	static const char oem[8] = "AMD     ";
@@ -33,7 +33,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 	mc->mpe_checksum = 0;
 	mc->reserved = 0;
 
-	smp_write_processors(mc, processor_map);
+	smp_write_processors(mc);
 
 	{
 		device_t dev;
@@ -82,24 +82,25 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 	smp_write_bus(mc, bus_isa, "ISA	  ");
 
 	/* IOAPIC handling */
-
 	smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
 	{
 		device_t dev;
-		uint32_t base;
+		struct resource *res;
 		/* 8131 apic 3 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
 		if (dev) {
-			base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-			base &= PCI_BASE_ADDRESS_MEM_MASK;
-			smp_write_ioapic(mc, 0x03, 0x11, base);
+			res = find_resource(dev, PCI_BASE_ADDRESS_0);
+			if (res) {
+				smp_write_ioapic(mc, 0x03, 0x11, res->base);
+			}
 		}
 		/* 8131 apic 4 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
 		if (dev) {
-			base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-			base &= PCI_BASE_ADDRESS_MEM_MASK;
-			smp_write_ioapic(mc, 0x04, 0x11, base);
+			res = find_resource(dev, PCI_BASE_ADDRESS_0);
+			if (res) {
+				smp_write_ioapic(mc, 0x04, 0x11, res->base);
+			}
 		}
 	}
 
@@ -216,17 +217,16 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 	printk_debug("Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
 
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
 	v = smp_write_floating_table(addr);
-	return (unsigned long)smp_write_config_table(v, processor_map);
+	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/amd/serenade/Config.lb b/src/mainboard/amd/serenade/Config.lb
index 79427896c5..4fbf6310b0 100644
--- a/src/mainboard/amd/serenade/Config.lb
+++ b/src/mainboard/amd/serenade/Config.lb
@@ -46,22 +46,22 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c" 
-	action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+	depends "$(MAINBOARD)/failover.c ./romcc" 
+	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "./failover.E ./romcc"
-	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+	depends "$(MAINBOARD)/failover.c ./romcc"
+	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h" 
-	action	"$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
+	action	"./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "./auto.E ./romcc"
-	action	"./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##
@@ -76,11 +76,11 @@ ldscript /cpu/x86/32bit/entry32.lds
 ## Build our reset vector (This is where linuxBIOS is entered)
 ##
 if USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
 else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
 end
 
 ### Should this be in the northbridge code?
diff --git a/src/mainboard/amd/serenade/auto.c b/src/mainboard/amd/serenade/auto.c
index 85ee737fd1..fb595f7acd 100644
--- a/src/mainboard/amd/serenade/auto.c
+++ b/src/mainboard/amd/serenade/auto.c
@@ -6,7 +6,8 @@
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -15,13 +16,15 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/cpu_rev.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -41,6 +44,10 @@ static void soft_reset(void)
 	pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
 }
 
+/*
+ * GPIO16 of 8111 will control H0_MEMRESET_L
+ * GPIO17 of 8111 will control H1_MEMRESET_L
+ */
 static void memreset_setup(void)
 {
 	if (is_cpu_pre_c0()) {
@@ -126,12 +133,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define FIRST_CPU  1
 #define SECOND_CPU 1
 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(void)
+static void main(unsigned long bist)
 {
-	/*
-	 * GPIO28 of 8111 will control H0_MEMRESET_L
-	 * GPIO29 of 8111 will control H1_MEMRESET_L
-	 */
 	static const struct mem_controller cpu[] = {
 #if FIRST_CPU
 		{
@@ -156,24 +159,31 @@ static void main(void)
 		},
 #endif
 	};
-	int needs_reset;
-
-	enable_lapic();
-	init_timer();
-
-	if (cpu_init_detected()) {
-		asm("jmp __cpu_reset");
-	}
 
-	distinguish_cpu_resets();
-	if (!boot_cpu()) {
-		stop_this_cpu();
+	int needs_reset;
+	if (bist == 0) {
+		/* Skip this if there was a built in self test failure */
+		amd_early_mtrr_init();
+		enable_lapic();
+		init_timer();
+		/* Has this cpu already booted? */
+		if (cpu_init_detected()) {
+			asm volatile ("jmp __cpu_reset");
+		}
+
+		distinguish_cpu_resets();
+		if (!boot_cpu()) {
+			stop_this_cpu();
+		}
 	}
-
+	/* Setup the console */
         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 	uart_init();
 	console_init();
 
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
 #if 0
 	print_pci_devices();
 #endif
diff --git a/src/mainboard/amd/serenade/chip.h b/src/mainboard/amd/serenade/chip.h
index 066852b37a..9f244772d0 100644
--- a/src/mainboard/amd/serenade/chip.h
+++ b/src/mainboard/amd/serenade/chip.h
@@ -1,4 +1,4 @@
-extern struct chip_operations mainboard_amd_serenade_control;
+extern struct chip_operations mainboard_amd_serenade_ops;
 
 struct mainboard_amd_serenade_config {
 	int nothing;
diff --git a/src/mainboard/amd/serenade/mainboard.c b/src/mainboard/amd/serenade/mainboard.c
index 750438ce28..ab3a800b52 100644
--- a/src/mainboard/amd/serenade/mainboard.c
+++ b/src/mainboard/amd/serenade/mainboard.c
@@ -3,11 +3,8 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-
-#include <arch/io.h>
-#include "../../../northbridge/amd/amdk8/northbridge.h"
 #include "chip.h"
 
-struct chip_operations mainboard_amd_serenade_control = {
-	.name      = "AMD Serenade mainboard ",
+struct chip_operations mainboard_amd_serenade_ops = {
+	CHIP_NAME("AMD Serenade mainboard ")
 };
diff --git a/src/mainboard/amd/serenade/mptable.c b/src/mainboard/amd/serenade/mptable.c
index 6e3b6e2557..b00eb2b082 100644
--- a/src/mainboard/amd/serenade/mptable.c
+++ b/src/mainboard/amd/serenade/mptable.c
@@ -4,7 +4,7 @@
 #include <string.h>
 #include <stdint.h>
 
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
 	static const char oem[8] = "AMD     ";
@@ -35,7 +35,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 	mc->mpe_checksum = 0;
 	mc->reserved = 0;
 
-	smp_write_processors(mc, processor_map);
+	smp_write_processors(mc);
 
 	{
 		device_t dev;
@@ -83,20 +83,22 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 	smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
 	{
 		device_t dev;
-		uint32_t base;
+		struct resource *res;
 		/* 8131-1 apic #3 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
 		if (dev) {
-			base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-			base &= PCI_BASE_ADDRESS_MEM_MASK;
-			smp_write_ioapic(mc, 0x03, 0x11, base);
+			res = find_resource(dev, PCI_BASE_ADDRESS_0);
+			if (res) {
+				smp_write_ioapic(mc, 0x03, 0x11, res->base);
+			}
 		}
 		/* 8131-2 apic #4 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
  		if (dev) {
-			base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-			base &= PCI_BASE_ADDRESS_MEM_MASK;
-			smp_write_ioapic(mc, 0x04, 0x11, base);
+			res = find_resource(dev, PCI_BASE_ADDRESS_0);
+			if (res) {
+				smp_write_ioapic(mc, 0x04, 0x11, res->base);
+			}
 		}
 	}
 
@@ -164,10 +166,10 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 	return smp_next_mpe_entry(mc);
 }
 
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
 	v = smp_write_floating_table(addr);
-	return (unsigned long)smp_write_config_table(v, processor_map);
+	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/amd/solo/Config.lb b/src/mainboard/amd/solo/Config.lb
index ad8bad9325..7f845725e3 100644
--- a/src/mainboard/amd/solo/Config.lb
+++ b/src/mainboard/amd/solo/Config.lb
@@ -47,22 +47,22 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c" 
-	action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+	depends "$(MAINBOARD)/failover.c ./romcc" 
+	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "./failover.E ./romcc"
-	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+	depends "$(MAINBOARD)/failover.c ./romcc"
+	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h " 
-	action	"$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
+	action	"./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "./auto.E ./romcc"
-	action	"./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##
diff --git a/src/mainboard/amd/solo/mainboard.c b/src/mainboard/amd/solo/mainboard.c
index 41ee605695..058a1aff01 100644
--- a/src/mainboard/amd/solo/mainboard.c
+++ b/src/mainboard/amd/solo/mainboard.c
@@ -4,30 +4,8 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-
-#include <arch/io.h>
-#include "../../../northbridge/amd/amdk8/northbridge.h"
 #include "chip.h"
 
-static void mainboard_init(device_t dev)
-{
-	root_dev_init(dev);
-}
-
-static struct device_operations mainboard_operations = {
-	.read_resources   = root_dev_read_resources,
-	.set_resources    = root_dev_set_resources,
-	.enable_resources = root_dev_enable_resources,
-	.init             = mainboard_init,
-	.scan_bus         = root_dev_scan_bus,
-	.enable = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
-	dev->ops = &mainboard_operations;
-}
-
 struct chip_operations mainboard_amd_solo_ops = {
-	.enable_dev = enable_dev,
+	CHIP_NAME("AMD Solo7 mainboard")
 };