AGESA boards: Clean up Ids.h and Filecode.h includes

Change-Id: I9cb63ff58900a39d7cd8e3da2b9a9a95c2a41a69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

32 files changed, 0 insertions, 51 deletions

diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c
index 4f66fad616..f14365ce66 100644
--- a/src/mainboard/amd/bettong/BiosCallOuts.c
+++ b/src/mainboard/amd/bettong/BiosCallOuts.c
@@ -19,7 +19,6 @@
 #include "amdlib.h"
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <northbridge/amd/pi/00660F01/chip.h>
-#include "Ids.h"
 #include "FchPlatform.h"
 #include "cbfs.h"
 #include "imc.h"
diff --git a/src/mainboard/amd/bettong/OemCustomize.c b/src/mainboard/amd/bettong/OemCustomize.c
index 8d1ad4bdb5..f26bf474dd 100644
--- a/src/mainboard/amd/bettong/OemCustomize.c
+++ b/src/mainboard/amd/bettong/OemCustomize.c
@@ -17,7 +17,6 @@
 #include <PlatformMemoryConfiguration.h>
 #include <boardid.h>
 
-#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
 
 static const PCIe_PORT_DESCRIPTOR PortList [] = {
 	/* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 3, ...) */
diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
index ceb295e5e4..71d3bd2dfc 100644
--- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
+++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
@@ -18,7 +18,6 @@
 #include "amdlib.h"
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <device/azalia.h>
-#include "Ids.h"
 #include "FchPlatform.h"
 #include "cbfs.h"
 #include "imc.h"
diff --git a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c
index bffe88896a..278d4974d0 100644
--- a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c
+++ b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c
@@ -17,7 +17,6 @@
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <PlatformMemoryConfiguration.h>
 
-#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
 
 static const PCIe_PORT_DESCRIPTOR PortList [] = {
 	/* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */
diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c
index e4ec12e4e1..d7cffd153f 100644
--- a/src/mainboard/amd/dinar/BiosCallOuts.c
+++ b/src/mainboard/amd/dinar/BiosCallOuts.c
@@ -17,7 +17,6 @@
 #include "amdlib.h"
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
-#include "Ids.h"
 #include "SB700.h"
 #include "OEM.h"		/* SMBUS0_BASE_ADDRESS */
 #include <stdlib.h>
diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c
index e237ff0b79..071b146e82 100644
--- a/src/mainboard/amd/dinar/buildOpts.c
+++ b/src/mainboard/amd/dinar/buildOpts.c
@@ -24,8 +24,6 @@
  */
 #include <stdlib.h>
 #include "AGESA.h"
-#include "Filecode.h"
-#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 //#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
 /* AGESA will check the OEM configuration during preprocessing stage,
  * coreboot enable -Wundef option, so we should make sure we have all contanstand defined
diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c
index affda6fd76..d1d2b864f5 100644
--- a/src/mainboard/amd/dinar/gpio.c
+++ b/src/mainboard/amd/dinar/gpio.c
@@ -13,12 +13,10 @@
  * GNU General Public License for more details.
  */
 
-#include "Filecode.h"
 #include "Hudson-2.h"
 #include "AmdSbLib.h"
 #include "gpio.h"
 
-#define FILECODE UNASSIGNED_FILE_FILECODE
 
 #ifndef SB_GPIO_REG01
 #define SB_GPIO_REG01   1
diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c
index e570e1e43d..7171b4c6ac 100644
--- a/src/mainboard/amd/inagua/OemCustomize.c
+++ b/src/mainboard/amd/inagua/OemCustomize.c
@@ -20,7 +20,6 @@
 #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
 #include <PlatformMemoryConfiguration.h>
 
-#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
 
 /*---------------------------------------------------------------------------------------*/
 /**
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index 1c5c424fdd..cc7d1efe05 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -26,8 +26,6 @@
  */
 
 #include <stdlib.h>
-#include "Filecode.h"
-#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
 /* Select the CPU family. */
diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c
index 88e529999e..4eda8d570d 100644
--- a/src/mainboard/amd/lamar/BiosCallOuts.c
+++ b/src/mainboard/amd/lamar/BiosCallOuts.c
@@ -16,7 +16,6 @@
 #include "AGESA.h"
 #include "amdlib.h"
 #include <northbridge/amd/agesa/BiosCallOuts.h>
-#include "Ids.h"
 #include "FchPlatform.h"
 #include "cbfs.h"
 #include "imc.h"
diff --git a/src/mainboard/amd/lamar/OemCustomize.c b/src/mainboard/amd/lamar/OemCustomize.c
index e2c9a6993a..32f8c23a81 100644
--- a/src/mainboard/amd/lamar/OemCustomize.c
+++ b/src/mainboard/amd/lamar/OemCustomize.c
@@ -16,7 +16,6 @@
 
 #include <northbridge/amd/pi/agesawrapper.h>
 
-#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
 
 static const PCIe_PORT_DESCRIPTOR PortList [] = {
 
diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c
index ad81edf152..e56f552baa 100644
--- a/src/mainboard/amd/olivehill/BiosCallOuts.c
+++ b/src/mainboard/amd/olivehill/BiosCallOuts.c
@@ -17,7 +17,6 @@
 #include "amdlib.h"
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include "Ids.h"
 #include "FchPlatform.h"
 #include "cbfs.h"
 #include "imc.h"
diff --git a/src/mainboard/amd/olivehill/OemCustomize.c b/src/mainboard/amd/olivehill/OemCustomize.c
index b0aa33ba28..d8171adb7b 100644
--- a/src/mainboard/amd/olivehill/OemCustomize.c
+++ b/src/mainboard/amd/olivehill/OemCustomize.c
@@ -15,14 +15,11 @@
 
 #include "AGESA.h"
 #include "amdlib.h"
-#include "Ids.h"
 #include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
-#include "Filecode.h"
 
 #include <northbridge/amd/agesa/state_machine.h>
 
-#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
 
 static const PCIe_PORT_DESCRIPTOR PortList [] = {
 	{
diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c
index 1d3fe778b0..b4afa30470 100644
--- a/src/mainboard/amd/olivehill/buildOpts.c
+++ b/src/mainboard/amd/olivehill/buildOpts.c
@@ -27,8 +27,6 @@
 
 #include <stdlib.h>
 #include "AGESA.h"
-#include "Filecode.h"
-#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 #define INSTALL_FT3_SOCKET_SUPPORT           TRUE
 #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT   TRUE
diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
index 49bc40224d..c6ed492adc 100644
--- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c
+++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
@@ -16,7 +16,6 @@
 #include "AGESA.h"
 #include "amdlib.h"
 #include <northbridge/amd/agesa/BiosCallOuts.h>
-#include "Ids.h"
 #include "FchPlatform.h"
 #include "cbfs.h"
 #include "imc.h"
diff --git a/src/mainboard/amd/olivehillplus/OemCustomize.c b/src/mainboard/amd/olivehillplus/OemCustomize.c
index ac60c42082..0511653e1a 100644
--- a/src/mainboard/amd/olivehillplus/OemCustomize.c
+++ b/src/mainboard/amd/olivehillplus/OemCustomize.c
@@ -15,7 +15,6 @@
 
 #include <northbridge/amd/pi/agesawrapper.h>
 
-#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
 
 static const PCIe_PORT_DESCRIPTOR PortList [] = {
 	/* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */
diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c
index dd7c6dd4b6..7a10ad9888 100644
--- a/src/mainboard/amd/parmer/BiosCallOuts.c
+++ b/src/mainboard/amd/parmer/BiosCallOuts.c
@@ -17,7 +17,6 @@
 #include "amdlib.h"
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include "Ids.h"
 #include "FchPlatform.h"
 #include "cbfs.h"
 #include "imc.h"
diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c
index c16e6d96bb..494215f0fe 100644
--- a/src/mainboard/amd/parmer/OemCustomize.c
+++ b/src/mainboard/amd/parmer/OemCustomize.c
@@ -15,14 +15,11 @@
 
 #include "AGESA.h"
 #include "amdlib.h"
-#include "Ids.h"
 #include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
-#include "Filecode.h"
 
 #include <northbridge/amd/agesa/state_machine.h>
 
-#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
 
 /*
  * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
index 49a9feb7a9..795112ca97 100644
--- a/src/mainboard/amd/parmer/buildOpts.c
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -27,8 +27,6 @@
 
 #include <stdlib.h>
 #include "AGESA.h"
-#include "Filecode.h"
-#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 /*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c
index c0dceff5af..e048e6c92e 100644
--- a/src/mainboard/amd/persimmon/OemCustomize.c
+++ b/src/mainboard/amd/persimmon/OemCustomize.c
@@ -20,7 +20,6 @@
 #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
 #include <PlatformMemoryConfiguration.h>
 
-#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
 
 /**
  *	OemCustomizeInitEarly
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index 670010d4c9..3fed0edeb7 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -26,8 +26,6 @@
  */
 
 #include <stdlib.h>
-#include "Filecode.h"
-#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
 /*	Select the CPU family.	*/
diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c
index a631eb0762..1f5297aedb 100644
--- a/src/mainboard/amd/south_station/OemCustomize.c
+++ b/src/mainboard/amd/south_station/OemCustomize.c
@@ -20,7 +20,6 @@
 #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
 #include <PlatformMemoryConfiguration.h>
 
-#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
 
 /*---------------------------------------------------------------------------------------*/
 /**
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index 38a272d6d7..542d5b6f5b 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -26,8 +26,6 @@
  */
 
 #include <stdlib.h>
-#include "Filecode.h"
-#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
 /*  Select the CPU family.  */
diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c
index 3ab174c609..f161e3867a 100644
--- a/src/mainboard/amd/thatcher/BiosCallOuts.c
+++ b/src/mainboard/amd/thatcher/BiosCallOuts.c
@@ -17,7 +17,6 @@
 #include "amdlib.h"
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include "Ids.h"
 #include "FchPlatform.h"
 #include "cbfs.h"
 #include "imc.h"
diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c
index 3f2563b606..f91bf2ab00 100644
--- a/src/mainboard/amd/thatcher/OemCustomize.c
+++ b/src/mainboard/amd/thatcher/OemCustomize.c
@@ -15,14 +15,11 @@
 
 #include "AGESA.h"
 #include "amdlib.h"
-#include "Ids.h"
 #include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
-#include "Filecode.h"
 
 #include <northbridge/amd/agesa/state_machine.h>
 
-#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
 
 /*
  * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c
index 7bc5a7789c..2f0b7ca37f 100644
--- a/src/mainboard/amd/thatcher/buildOpts.c
+++ b/src/mainboard/amd/thatcher/buildOpts.c
@@ -27,8 +27,6 @@
 
 #include <stdlib.h>
 #include "AGESA.h"
-#include "Filecode.h"
-#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 /*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c
index 38206ff4a2..3e3d2520e2 100644
--- a/src/mainboard/amd/torpedo/BiosCallOuts.c
+++ b/src/mainboard/amd/torpedo/BiosCallOuts.c
@@ -16,7 +16,6 @@
 #include "AGESA.h"
 #include "amdlib.h"
 #include <northbridge/amd/agesa/BiosCallOuts.h>
-#include "Ids.h"
 #include "Hudson-2.h"
 #include <stdlib.h>
 #include <southbridge/amd/cimx/sb700/gpio_oem.h>
diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c
index 8dc5affb63..196e8bbaa4 100644
--- a/src/mainboard/amd/torpedo/OemCustomize.c
+++ b/src/mainboard/amd/torpedo/OemCustomize.c
@@ -21,7 +21,6 @@
 #include <PlatformMemoryConfiguration.h>
 #include "amdlib.h"
 
-#define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE
 
 static const PCIe_PORT_DESCRIPTOR PortList [] = {
 	// Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c
index 656102d015..07850d60df 100644
--- a/src/mainboard/amd/torpedo/buildOpts.c
+++ b/src/mainboard/amd/torpedo/buildOpts.c
@@ -27,8 +27,6 @@
 
 #include <stdlib.h>
 #include "AGESA.h"
-#include "Filecode.h"
-#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
 /*  Select the CPU family.  */
diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c
index 03ab409a6c..5a77dc0de0 100644
--- a/src/mainboard/amd/torpedo/gpio.c
+++ b/src/mainboard/amd/torpedo/gpio.c
@@ -13,12 +13,10 @@
  * GNU General Public License for more details.
  */
 
-#include "Filecode.h"
 #include "SbPlatform.h"
 #include "gpio.h"
 #include "vendorcode/amd/cimx/sb900/AmdSbLib.h"
 
-#define FILECODE UNASSIGNED_FILE_FILECODE
 
 #ifndef SB_GPIO_REG01
 #define SB_GPIO_REG01   1
diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c
index 00db12c88e..6f9b3b49f4 100644
--- a/src/mainboard/amd/union_station/OemCustomize.c
+++ b/src/mainboard/amd/union_station/OemCustomize.c
@@ -15,16 +15,13 @@
 
 #include "AGESA.h"
 #include "amdlib.h"
-#include "Ids.h"
 #include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
 #include "PlatformGnbPcieComplex.h"
-#include "Filecode.h"
 
 #include <string.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
-#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
 
 /*---------------------------------------------------------------------------------------*/
 /**
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index 38a272d6d7..542d5b6f5b 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -26,8 +26,6 @@
  */
 
 #include <stdlib.h>
-#include "Filecode.h"
-#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
 /*  Select the CPU family.  */