src/mainboard: Capitalize ROM, RAM, CPU and APIC

Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15987
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

25 files changed, 33 insertions, 33 deletions

diff --git a/src/mainboard/amd/db-ft3b-lc/Makefile.inc b/src/mainboard/amd/db-ft3b-lc/Makefile.inc
index 8b160e26f4..97c761fa45 100644
--- a/src/mainboard/amd/db-ft3b-lc/Makefile.inc
+++ b/src/mainboard/amd/db-ft3b-lc/Makefile.inc
@@ -27,7 +27,7 @@ SPD_SOURCES  = Memphis_MEM4G16D3EABG
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/amd/db800/irq_tables.c b/src/mainboard/amd/db800/irq_tables.c
index 00a19dba66..8cf172a540 100644
--- a/src/mainboard/amd/db800/irq_tables.c
+++ b/src/mainboard/amd/db800/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{
 	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
+	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* CPU */
 	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
 	 {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* ethernet */
 	 {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0},	/* slot1 */
diff --git a/src/mainboard/amd/dbm690t/fadt.c b/src/mainboard/amd/dbm690t/fadt.c
index 4afb0b9e4c..f9768b20bd 100644
--- a/src/mainboard/amd/dbm690t/fadt.c
+++ b/src/mainboard/amd/dbm690t/fadt.c
@@ -25,7 +25,7 @@
 #include "southbridge/amd/sb600/sb600.h"
 
 /*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
 /* pm_base should be got from bar2 of rs690. Here I compact ACPI
  * registers into 32 bytes limit.
  * */
diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c
index 3fd9c48885..e237ff0b79 100644
--- a/src/mainboard/amd/dinar/buildOpts.c
+++ b/src/mainboard/amd/dinar/buildOpts.c
@@ -54,10 +54,10 @@
 #define POWER_DOWN_BY_CHANNEL		0	///< Channel power down mode
 #define POWER_DOWN_BY_CHIP_SELECT	1	///< Chip select power down mode
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  TRUE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index 70cd5e3586..bc5d3126f2 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 
 	post_code(0x43);
-	printk(BIOS_DEBUG, "Disabling cache as ram ");
+	printk(BIOS_DEBUG, "Disabling cache as RAM ");
 	disable_cache_as_ram();
 	printk(BIOS_DEBUG, "done\n");
 
diff --git a/src/mainboard/amd/f2950/irq_tables.c b/src/mainboard/amd/f2950/irq_tables.c
index b438f0246e..dae29a142f 100644
--- a/src/mainboard/amd/f2950/irq_tables.c
+++ b/src/mainboard/amd/f2950/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{
 	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
+	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* CPU */
 	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
 	 {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},   /* ethernet */
 	 }
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index 361531e612..1c5c424fdd 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -30,13 +30,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/* Select the cpu family. */
+/* Select the CPU family. */
 #define INSTALL_FAMILY_10_SUPPORT		FALSE
 #define INSTALL_FAMILY_12_SUPPORT		FALSE
 #define INSTALL_FAMILY_14_SUPPORT		TRUE
 #define INSTALL_FAMILY_15_SUPPORT		FALSE
 
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
 #define INSTALL_G34_SOCKET_SUPPORT		FALSE
 #define INSTALL_C32_SOCKET_SUPPORT 		FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT		FALSE
diff --git a/src/mainboard/amd/norwich/irq_tables.c b/src/mainboard/amd/norwich/irq_tables.c
index dfb1ef4d08..a59dc26df7 100644
--- a/src/mainboard/amd/norwich/irq_tables.c
+++ b/src/mainboard/amd/norwich/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{
 	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
+	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* CPU */
 	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
 	 {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0},	/* slot1 */
 	 {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0},	/* slot2 */
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
index 25cec3b0b6..8ba3c539ba 100644
--- a/src/mainboard/amd/parmer/buildOpts.c
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -30,13 +30,13 @@
 #include "Filecode.h"
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index eb6cf33fa4..670010d4c9 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -30,13 +30,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*	Select the cpu family.	*/
+/*	Select the CPU family.	*/
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*	Select the cpu socket type.	*/
+/*	Select the CPU socket type.	*/
 #define INSTALL_G34_SOCKET_SUPPORT	FALSE
 #define INSTALL_C32_SOCKET_SUPPORT	FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/pistachio/fadt.c b/src/mainboard/amd/pistachio/fadt.c
index 4afb0b9e4c..f9768b20bd 100644
--- a/src/mainboard/amd/pistachio/fadt.c
+++ b/src/mainboard/amd/pistachio/fadt.c
@@ -25,7 +25,7 @@
 #include "southbridge/amd/sb600/sb600.h"
 
 /*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
 /* pm_base should be got from bar2 of rs690. Here I compact ACPI
  * registers into 32 bytes limit.
  * */
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl
index cc9b65bfc9..aaa778b7ee 100644
--- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl
+++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl
@@ -61,7 +61,7 @@
 
             Device (SBC3)
             {
-                /*  acpi smbus   it should be 0x00040003 if 8131 present */
+                /*  ACPI smbus   it should be 0x00040003 if 8131 present */
 		Method (_ADR, 0, NotSerialized)
 		{
 			Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c
index 4fe4efd0ce..bd0096152b 100644
--- a/src/mainboard/amd/serengeti_cheetah/fadt.c
+++ b/src/mainboard/amd/serengeti_cheetah/fadt.c
@@ -21,7 +21,7 @@
 #include <console/console.h>
 #include <arch/acpi.h>
 
-extern unsigned pm_base; /* pm_base should be set in sb acpi */
+extern unsigned pm_base; /* pm_base should be set in sb ACPI */
 
 void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 
diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
index 0492e9a5c5..1eb97b59a7 100644
--- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
@@ -77,7 +77,7 @@ static unsigned get_hcid(unsigned i)
 
 	// we may need more way to find out hcid: subsystem id? GPIO read ?
 
-	// we need use id for 1. bus num, 2. mptable, 3. acpi table
+	// we need use id for 1. bus num, 2. mptable, 3. ACPI table
 
 	return id;
 }
diff --git a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
index b999dfacbf..0dbf303935 100644
--- a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
+++ b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
@@ -1,4 +1,4 @@
-At this time, For acpi support We got
+At this time, For ACPI support We got
 1. support AMK K8 SRAT --- dynamically (coreboot run-time)  (src/northbridge/amd/amdk8/amdk8_acpi.c)
 2. support MADT ---- dynamically (coreboot run-time)  (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
 3. support DSDT ---- dynamically (Compile time, coreboot run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{acpi/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index ded74a5e25..51fce316a7 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -224,5 +224,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 #endif
 
-        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+        post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
 }
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl
index 46fe1216b8..f6a1954aa1 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl
@@ -53,7 +53,7 @@
 
 	Device (SBC3)
 	{
-		// acpi smbus it should be 0x00040003 if 8131 present
+		// ACPI smbus it should be 0x00040003 if 8131 present
 		Method (_ADR, 0, NotSerialized)
 		{
 			Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
index 544df8ef8f..3183a7ebcc 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
@@ -24,7 +24,7 @@
 #include <console/console.h>
 #include <arch/acpi.h>
 
-extern u32 pm_base; /* pm_base should be set in sb acpi */
+extern u32 pm_base; /* pm_base should be set in sb ACPI */
 
 void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
index 6113f0e097..66dee1831d 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
@@ -81,7 +81,7 @@ static u32 get_hcid(u32 i)
 		break;
 	}
 	// we may need more way to find out hcid: subsystem id? GPIO read ?
-	// we need use id for 1. bus num, 2. mptable, 3. acpi table
+	// we need use id for 1. bus num, 2. mptable, 3. ACPI table
 	return id;
 }
 
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index 2b411e7792..38a272d6d7 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -30,13 +30,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c
index 4da5f5f266..8ed3bf2fdc 100644
--- a/src/mainboard/amd/thatcher/buildOpts.c
+++ b/src/mainboard/amd/thatcher/buildOpts.c
@@ -30,13 +30,13 @@
 #include "Filecode.h"
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c
index e0ee622dbf..d81748af92 100644
--- a/src/mainboard/amd/torpedo/buildOpts.c
+++ b/src/mainboard/amd/torpedo/buildOpts.c
@@ -31,13 +31,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT TRUE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c
index 9a615c119b..fba8fc83cd 100644
--- a/src/mainboard/amd/torpedo/fadt.c
+++ b/src/mainboard/amd/torpedo/fadt.c
@@ -27,7 +27,7 @@
 #include "SbPlatform.h"
 
 /*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
 /* pm_base should be got from bar2 of sb900. Here I compact ACPI
  * registers into 32 bytes limit.
  * */
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index bf551a9ffc..c5c908de9c 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -77,7 +77,7 @@ static void *smp_write_config_table(void *v)
   mptable_init(mc, LOCAL_APIC_ADDR);
   memcpy(mc->mpc_oem, "AMD     ", 8);
 
-  /*Inagua used dure core cpu with one die */
+  /*Inagua used dure core CPU with one die */
   boot_apic_id = lapicid();
   apic_version = lapic_read(LAPIC_LVR) & 0xff;
   result = cpuid(1);
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index 2b411e7792..38a272d6d7 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -30,13 +30,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE