diff options
| author | Timothy Pearson <tpearson@raptorengineering.com> | 2017-01-04 14:26:26 -0600 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineering.com> | 2017-01-05 21:53:55 +0100 |
| commit | 7ad4dc5e9914e927a827ce48a030d2d04e7ec792 (patch) | |
| tree | 1a279d488f9730ff954a7783dfde95c275c1a09c /src/mainboard/amd | |
| parent | d502dc092a26726472fc5871c77ebff192be4cb8 (diff) | |
src/amd: Add common definition of AMD ACPI MMIO address
The bare ACPI MMIO address 0xFED80000 was used in multiple
AMD mainboard files as well as the SB800 native code. Reduce
duplication by using a centrally defined value for all AMD
ACPI MMIO access.
Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18032
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/bettong/boardid.c | 3 | ||||
| -rw-r--r-- | src/mainboard/amd/bimini_fam10/mainboard.c | 5 | ||||
| -rw-r--r-- | src/mainboard/amd/lamar/romstage.c | 5 |
3 files changed, 8 insertions, 5 deletions
diff --git a/src/mainboard/amd/bettong/boardid.c b/src/mainboard/amd/bettong/boardid.c index ae33328c1f..4b2dceb375 100644 --- a/src/mainboard/amd/bettong/boardid.c +++ b/src/mainboard/amd/bettong/boardid.c @@ -15,6 +15,7 @@ #include <stdint.h> #include <arch/io.h> +#include <southbridge/amd/common/amd_defs.h> #include <boardid.h> /** @@ -34,7 +35,7 @@ uint8_t board_id(void) u8 boardrev = 0; char boardid; - gpiommioaddr = (void *)0xfed80000ul + 0x1500; + gpiommioaddr = (void *)AMD_SB_ACPI_MMIO_ADDR + 0x1500; value = read8(gpiommioaddr + (7 << 2) + 2); /* agpio7: board_id2 */ boardrev = value & 1; value = read8(gpiommioaddr + (6 << 2) + 2); /* agpio6: board_id1 */ diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index c4dd21e78f..d10f0dbad6 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -20,6 +20,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> +#include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/sb800/sb800.h> @@ -45,12 +46,12 @@ void enable_int_gfx(void) byte |= 1; pm_iowrite(0x24, byte); - gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */ + gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0xD00; /* IoMux Register */ *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */ *(gpio_reg + 170) = 0x1; /* gpio_gate */ - gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */ + gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0x100; /* GPIO Registers */ *(gpio_reg + 0x6) = 0x8; *(gpio_reg + 170) = 0x0; diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 58c6e42e39..bda8c0fe61 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -30,6 +30,7 @@ #include <northbridge/amd/pi/agesawrapper_call.h> #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> +#include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> #include "cbmem.h" @@ -59,8 +60,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0x24, 0xCD6); outb(0x01, 0xCD7); - *(volatile u32 *) (0xFED80000 + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ - *(volatile u32 *) (0xFED80000 + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ + *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ + *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ hudson_lpc_port80(); |