- move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1

- move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges
- drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 5 insertions, 24 deletions

diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index f7f40536f4..9635e39fd0 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -51,10 +51,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 16ea5f204f..702b97965e 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -50,11 +50,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index d5a907c64e..64e02f49e0 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -59,11 +59,7 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index a3909f4799..51269b1cf6 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -45,11 +45,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 1e331fe717..b0da2aec6c 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -59,11 +59,7 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>