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authorRonald G. Minnich <rminnich@gmail.com>2006-04-10 16:40:19 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-04-10 16:40:19 +0000
commit45f6c5e3d450053e53a8ff4a687fd0dcaf2d7475 (patch)
tree8cf49ad51549655c749bc7bc8edd98de41bd604e /src/mainboard/amd
parent526b2c429e41bbd177853169deb63c1bf00c70a9 (diff)
add cpureginit to romcc code.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/rumba/auto.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index 3ac8fd2797..dae503b696 100644
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -100,6 +100,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
#include "northbridge/amd/gx2/pll_reset.c"
+#include "cpu/amd/model_gx2/cpureginit.c"
static void msr_init(void)
{
@@ -153,8 +154,8 @@ static void main(unsigned long bist)
pll_reset();
- /* Halt if there was a built in self test failure */
- //report_bist_failure(bist);
+ cpuRegInit();
+ print_err("done cpuRegInit\n");
sdram_initialize(1, memctrl);