mainboard/*/*/mptable.c: Improve code formatting

Change-Id: I341293cd334d6d465636db7e81400230d61bc693
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16723
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

10 files changed, 412 insertions, 412 deletions

diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c
index 1c74ae5359..744fd985e3 100644
--- a/src/mainboard/amd/bettong/mptable.c
+++ b/src/mainboard/amd/bettong/mptable.c
@@ -84,7 +84,7 @@ static void *smp_write_config_table(void *v)
 	 * associated with a specific bus/device/function tuple.
 	 */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
 
 	/* Internal VGA */
 	PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
diff --git a/src/mainboard/amd/db-ft3b-lc/mptable.c b/src/mainboard/amd/db-ft3b-lc/mptable.c
index 0c668df1ca..dac38976c4 100644
--- a/src/mainboard/amd/db-ft3b-lc/mptable.c
+++ b/src/mainboard/amd/db-ft3b-lc/mptable.c
@@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v)
 	 * associated with a specific bus/device/function tuple.
 	 */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
 
 	/* APU Internal Graphic Device */
 	PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index 50d1aa322d..9ae75aee08 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -150,7 +150,7 @@ static void *smp_write_config_table(void *v)
 	 * associated with a specific bus/device/function tuple.
 	 */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
 
 	/* Internal VGA */
 	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c
index a2ba7f4e76..925526c689 100644
--- a/src/mainboard/amd/olivehillplus/mptable.c
+++ b/src/mainboard/amd/olivehillplus/mptable.c
@@ -111,7 +111,7 @@ static void *smp_write_config_table(void *v)
 	 * associated with a specific bus/device/function tuple.
 	 */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
 
 	/* Internal VGA */
 	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index 8f226d54d1..e10fc8911d 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -111,7 +111,7 @@ static void *smp_write_config_table(void *v)
 	 * associated with a specific bus/device/function tuple.
 	 */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
 
 	/* Internal VGA */
 	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index acc4a6c68c..2ffe4c9070 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -25,15 +25,15 @@
 
 static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
 	int i, j, bus_isa;
 	struct mb_sysconf_t *m;
 
-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);
 
-        smp_write_processors(mc);
+	smp_write_processors(mc);
 
 	get_bus_conf();
 
@@ -43,54 +43,54 @@ static void *smp_write_config_table(void *v)
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
 	smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
-        {
-                device_t dev;
+	{
+		device_t dev;
 		struct resource *res;
-                dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
-                if (dev) {
+		dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
+		if (dev) {
 			res = find_resource(dev, PCI_BASE_ADDRESS_0);
 			if (res) {
 				smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
 						 res2mmio(res, 0, 0));
 			}
-                }
-                dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
-                if (dev) {
+		}
+		dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
+		if (dev) {
 			res = find_resource(dev, PCI_BASE_ADDRESS_0);
 			if (res) {
 				smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
 						 res2mmio(res, 0, 0));
 			}
-                }
+		}
 
-                j = 0;
+		j = 0;
 
-                for(i = 1; i< sysconf.hc_possible_num; i++) {
-                        if(!(sysconf.pci1234[i] & 0x1) ) continue;
+		for(i = 1; i< sysconf.hc_possible_num; i++) {
+			if(!(sysconf.pci1234[i] & 0x1) ) continue;
 
-                        switch(sysconf.hcid[i]) {
-                        case 1: // 8132
+			switch(sysconf.hcid[i]) {
+			case 1: // 8132
 			case 3: // 8131
-                                dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
-                                if (dev) {
-                                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
-                                        if (res) {
-                                                smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
+				dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
+				if (dev) {
+					res = find_resource(dev, PCI_BASE_ADDRESS_0);
+					if (res) {
+						smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
 								 res2mmio(res, 0, 0));
-                                        }
-                                }
-                                dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
-                                if (dev) {
-                                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
-                                        if (res) {
-                                                smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
+					}
+				}
+				dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
+				if (dev) {
+					res = find_resource(dev, PCI_BASE_ADDRESS_0);
+					if (res) {
+						smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
 								 res2mmio(res, 0, 0));
-                                        }
-                                }
-                                break;
-                        }
-                        j++;
-                }
+					}
+				}
+				break;
+			}
+			j++;
+		}
 
 	}
 
@@ -98,76 +98,76 @@ static void *smp_write_config_table(void *v)
 
 /*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
 //??? What
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
 
 // Onboard AMD USB
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
 
 //Slot 3  PCI 32
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
+	}
 
 
 //Slot 4 PCI 32
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
+	}
 
 
 //Slot 1 PCI-X 133/100/66
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); //
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); //
+	}
 
 
 //Slot 2 PCI-X 133/100/66
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25
-        }
-
-        j = 0;
-
-        for(i = 1; i< sysconf.hc_possible_num; i++) {
-                if(!(sysconf.pci1234[i] & 0x1) ) continue;
-                int ii;
-                device_t dev;
-                struct resource *res;
-                switch(sysconf.hcid[i]) {
-                case 1:
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25
+	}
+
+	j = 0;
+
+	for(i = 1; i< sysconf.hc_possible_num; i++) {
+		if(!(sysconf.pci1234[i] & 0x1) ) continue;
+		int ii;
+		device_t dev;
+		struct resource *res;
+		switch(sysconf.hcid[i]) {
+		case 1:
 		case 3:
-                        dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
-                        if (dev) {
-                                res = find_resource(dev, PCI_BASE_ADDRESS_0);
-                                if (res) {
-                                        //Slot 1 PCI-X 133/100/66
-                                        for(ii = 0; ii < 4; ii++) {
-                                                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
-                                        }
-                                }
-                        }
-
-                        dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
-                        if (dev) {
-                                res = find_resource(dev, PCI_BASE_ADDRESS_0);
-                                if (res) {
-                                        //Slot 2 PCI-X 133/100/66
-                                        for(ii = 0; ii < 4; ii++) {
-                                                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
-                                        }
-                                }
-                        }
-
-                        break;
-                case 2:
-
-                //  Slot AGP
-                        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
-                        break;
-                }
-
-                j++;
-        }
+			dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
+			if (dev) {
+				res = find_resource(dev, PCI_BASE_ADDRESS_0);
+				if (res) {
+					//Slot 1 PCI-X 133/100/66
+					for(ii = 0; ii < 4; ii++) {
+						smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
+					}
+				}
+			}
+
+			dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
+			if (dev) {
+				res = find_resource(dev, PCI_BASE_ADDRESS_0);
+				if (res) {
+					//Slot 2 PCI-X 133/100/66
+					for(ii = 0; ii < 4; ii++) {
+						smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
+					}
+				}
+			}
+
+			break;
+		case 2:
+
+		//  Slot AGP
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
+			break;
+		}
+
+		j++;
+	}
 
 
 
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index 19a9f35b97..c24e42cf93 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -26,81 +26,81 @@
 
 
 u8 intr_data[] = {
-  [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
-  [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
-  [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x10,0x11,0x12,0x13
+	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
+	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x10,0x11,0x12,0x13
 };
 
 static void *smp_write_config_table(void *v)
 {
-  struct mp_config_table *mc;
-  int bus_isa;
+	struct mp_config_table *mc;
+	int bus_isa;
 
 	/*
 	 * By the time this function gets called, the IOAPIC registers
 	 * have been written so they can be read to get the correct
 	 * APIC ID and Version
 	 */
-  u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
-  u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
 
-  mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-  mptable_init(mc, LOCAL_APIC_ADDR);
-  memcpy(mc->mpc_oem, "AMD     ", 8);
+	mptable_init(mc, LOCAL_APIC_ADDR);
+	memcpy(mc->mpc_oem, "AMD     ", 8);
 
-  smp_write_processors(mc);
+	smp_write_processors(mc);
 
-  mptable_write_buses(mc, NULL, &bus_isa);
+	mptable_write_buses(mc, NULL, &bus_isa);
 
-  /* I/O APICs:   APIC ID Version State   Address */
+	/* I/O APICs:   APIC ID Version State   Address */
 	smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
 
-  u8 byte;
+	u8 byte;
 
-  for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-    outb(byte | 0x80, 0xC00);
-    outb(intr_data[byte], 0xC01);
-  }
+	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+		outb(byte | 0x80, 0xC00);
+		outb(intr_data[byte], 0xC01);
+	}
 
-  /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
-  smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
 
-  mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
 
-  /* PCI interrupts are level triggered, and are
-   * associated with a specific bus/device/function tuple.
-   */
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
 #define PCI_INT(bus, dev, fn, pin) \
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
 
-  /* APU Internal Graphic Device*/
-  PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
-  PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+	/* APU Internal Graphic Device*/
+	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
 
-  //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
-  PCI_INT(0x0, 0x14, 0x0, 0x10);
-  /* Southbridge HD Audio: */
-  PCI_INT(0x0, 0x14, 0x2, 0x12);
+	//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+	/* Southbridge HD Audio: */
+	PCI_INT(0x0, 0x14, 0x2, 0x12);
 
-  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
-  PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
-  PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
-  PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
-  PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
-  PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
+	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
 
-  /* sata */
-  PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
 
-  /* on board NIC & Slot PCIE.  */
+	/* on board NIC & Slot PCIE.  */
 
-  /* PCI slots */
+	/* PCI slots */
 	device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
@@ -123,27 +123,27 @@ static void *smp_write_config_table(void *v)
 		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
 	}
 
-  /* PCIe PortA */
-  PCI_INT(0x0, 0x15, 0x0, 0x10);
-  /* PCIe PortB */
-  PCI_INT(0x0, 0x15, 0x1, 0x11);
-  /* PCIe PortC */
-  PCI_INT(0x0, 0x15, 0x2, 0x12);
-  /* PCIe PortD */
-  PCI_INT(0x0, 0x15, 0x3, 0x13);
-
-  /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-  IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-  IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-  /* There is no extension information... */
-
-  /* Compute the checksums */
-  return mptable_finalize(mc);
+	/* PCIe PortA */
+	PCI_INT(0x0, 0x15, 0x0, 0x10);
+	/* PCIe PortB */
+	PCI_INT(0x0, 0x15, 0x1, 0x11);
+	/* PCIe PortC */
+	PCI_INT(0x0, 0x15, 0x2, 0x12);
+	/* PCIe PortD */
+	PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
 {
-  void *v;
-  v = smp_write_floating_table(addr, 0);
-  return (unsigned long)smp_write_config_table(v);
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index 797f679105..26402847b8 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -111,7 +111,7 @@ static void *smp_write_config_table(void *v)
 	 * associated with a specific bus/device/function tuple.
 	 */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
 
 	/* Internal VGA */
 	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index c5c908de9c..8091ffbc3d 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -25,210 +25,210 @@
 #include <cpu/amd/amdfam12.h>
 #include "SbPlatform.h"
 
-#define IO_APIC_ID    CONFIG_MAX_CPUS
+#define IO_APIC_ID CONFIG_MAX_CPUS
 u32 apicid_sb900;
 
 u8 picr_data[] = {
-  0x0B,0x0B,0x0B,0x0B,0x1F,0x1F,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-  0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x0B,0x0B,0x0B,0x0B
+	0x0B,0x0B,0x0B,0x0B,0x1F,0x1F,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+	0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x0B,0x0B,0x0B,0x0B
 };
 u8 intr_data[] = {
-  0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-  0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x10,0x11,0x12,0x13
+	0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+	0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x10,0x11,0x12,0x13
 };
 
 static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
 {
-  mc->mpc_length += length;
-  mc->mpc_entry_count++;
+	mc->mpc_length += length;
+	mc->mpc_entry_count++;
 }
 static void my_smp_write_bus(struct mp_config_table *mc,
-  unsigned char id, const char *bustype)
+	unsigned char id, const char *bustype)
 {
-  struct mpc_config_bus *mpc;
-  mpc = smp_next_mpc_entry(mc);
-  memset(mpc, '\0', sizeof(*mpc));
-  mpc->mpc_type = MP_BUS;
-  mpc->mpc_busid = id;
-  memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
-  smp_add_mpc_entry(mc, sizeof(*mpc));
+	struct mpc_config_bus *mpc;
+	mpc = smp_next_mpc_entry(mc);
+	memset(mpc, '\0', sizeof(*mpc));
+	mpc->mpc_type = MP_BUS;
+	mpc->mpc_busid = id;
+	memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+	smp_add_mpc_entry(mc, sizeof(*mpc));
 }
 static void *smp_write_config_table(void *v)
 {
-  struct mp_config_table *mc;
-  int bus_isa;
-  int boot_apic_id;
-  unsigned apic_version;
-  unsigned cpu_features;
-  unsigned cpu_feature_flags;
-  struct cpuid_result result;
-  unsigned long cpu_flag;
-
-  mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-  mptable_init(mc, LOCAL_APIC_ADDR);
-  memcpy(mc->mpc_oem, "AMD     ", 8);
-
-  /*Inagua used dure core CPU with one die */
-  boot_apic_id = lapicid();
-  apic_version = lapic_read(LAPIC_LVR) & 0xff;
-  result = cpuid(1);
-  cpu_features = result.eax;
-  cpu_feature_flags = result.edx;
-  cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
-  smp_write_processor(mc,
-      0, apic_version,
-      cpu_flag, cpu_features, cpu_feature_flags
-    );
-
-  cpu_flag = MPC_CPU_ENABLED;
-  smp_write_processor(mc,
-      1, apic_version,
-      cpu_flag, cpu_features, cpu_feature_flags
-    );
-
-  //mptable_write_buses(mc, NULL, &bus_isa);
-  my_smp_write_bus(mc, 0, "PCI   ");
-  my_smp_write_bus(mc, 1, "PCI   ");
-  bus_isa = 0x02;
-  my_smp_write_bus(mc, bus_isa, "ISA   ");
-
-  /* I/O APICs:   APIC ID Version State   Address */
-
-  u8 *dword;
-  u8 byte;
-
-  ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
-  dword = (u8 *)(((uintptr_t) dword) & 0xFFFFFFF0);
-  /* Set IO APIC ID onto IO_APIC_ID */
-  write32 (dword, 0x00);
-  write32 (dword + 0x10, IO_APIC_ID << 24);
-  apicid_sb900 = IO_APIC_ID;
-  smp_write_ioapic(mc, apicid_sb900, 0x21, dword);
-
-  /* PIC IRQ routine */
-  for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
-    outb(byte, 0xC00);
-    outb(picr_data[byte], 0xC01);
-  }
-
-  /* APIC IRQ routine */
-  for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-    outb(byte | 0x80, 0xC00);
-    outb(intr_data[byte], 0xC01);
-  }
-
-    /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	struct mp_config_table *mc;
+	int bus_isa;
+	int boot_apic_id;
+	unsigned apic_version;
+	unsigned cpu_features;
+	unsigned cpu_feature_flags;
+	struct cpuid_result result;
+	unsigned long cpu_flag;
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+	mptable_init(mc, LOCAL_APIC_ADDR);
+	memcpy(mc->mpc_oem, "AMD     ", 8);
+
+	/*Inagua used dure core CPU with one die */
+	boot_apic_id = lapicid();
+	apic_version = lapic_read(LAPIC_LVR) & 0xff;
+	result = cpuid(1);
+	cpu_features = result.eax;
+	cpu_feature_flags = result.edx;
+	cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
+	smp_write_processor(mc,
+	  0, apic_version,
+	  cpu_flag, cpu_features, cpu_feature_flags
+	);
+
+	cpu_flag = MPC_CPU_ENABLED;
+	smp_write_processor(mc,
+	  1, apic_version,
+	  cpu_flag, cpu_features, cpu_feature_flags
+	);
+
+	//mptable_write_buses(mc, NULL, &bus_isa);
+	my_smp_write_bus(mc, 0, "PCI   ");
+	my_smp_write_bus(mc, 1, "PCI   ");
+	bus_isa = 0x02;
+	my_smp_write_bus(mc, bus_isa, "ISA   ");
+
+	/* I/O APICs:   APIC ID Version State   Address */
+
+	u8 *dword;
+	u8 byte;
+
+	ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+	dword = (u8 *)(((uintptr_t) dword) & 0xFFFFFFF0);
+	/* Set IO APIC ID onto IO_APIC_ID */
+	write32 (dword, 0x00);
+	write32 (dword + 0x10, IO_APIC_ID << 24);
+	apicid_sb900 = IO_APIC_ID;
+	smp_write_ioapic(mc, apicid_sb900, 0x21, dword);
+
+	/* PIC IRQ routine */
+	for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+		outb(byte, 0xC00);
+		outb(picr_data[byte], 0xC01);
+	}
+
+	/* APIC IRQ routine */
+	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+		outb(byte | 0x80, 0xC00);
+		outb(intr_data[byte], 0xC01);
+	}
+
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
-  smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-  //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0);
-  /*I/O Ints:          Type    Trigger             Polarity               Bus ID   IRQ  APIC ID       PIN# */
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, apicid_sb900, 0x0);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_sb900, 0x1);
-  smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x2, apicid_sb900, 0x2);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, apicid_sb900, 0x3);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, apicid_sb900, 0x4);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  0, 0x49, apicid_sb900, 0x11);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, apicid_sb900, 0x6);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, apicid_sb900, 0x7);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, apicid_sb900, 0x8);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x9, apicid_sb900, 0x9);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0xa, apicid_sb900, 0xa);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0x1c, apicid_sb900, 0x13);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, apicid_sb900, 0xc);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, apicid_sb900, 0xd);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, apicid_sb900, 0xe);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_sb900, 0xf);
-
-  /* PCI interrupts are level triggered, and are
-   * associated with a specific bus/device/function tuple.
-   */
+	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+	//mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0);
+	/*I/O Ints:          Type    Trigger             Polarity               Bus ID   IRQ  APIC ID       PIN# */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, apicid_sb900, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_sb900, 0x1);
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x2, apicid_sb900, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, apicid_sb900, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, apicid_sb900, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  0, 0x49, apicid_sb900, 0x11);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, apicid_sb900, 0x6);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, apicid_sb900, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, apicid_sb900, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x9, apicid_sb900, 0x9);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0xa, apicid_sb900, 0xa);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0x1c, apicid_sb900, 0x13);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, apicid_sb900, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, apicid_sb900, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, apicid_sb900, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_sb900, 0xf);
+
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
 #define PCI_INT(bus, dev, int_sign, pin) \
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin))
-
-  /* Internal VGA */
-  PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
-  PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
-
-  /* SMBUS */
-  PCI_INT(0x0, 0x14, 0x0, 0x10);
-
-  /* HD Audio */
-  PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
-
-  /* USB */
-  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
-  PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
-  PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
-  PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
-  PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
-  PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
-  PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
-
-  /* sata */
-  PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
-  PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
-
-
-  /* on board NIC & Slot PCIE.  */
-
-  /* PCI slots */
-  device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-  if (dev && dev->enabled) {
-	  u8 bus_pci = dev->link_list->secondary;
-
-	  /* PCI_SLOT 0. */
-	  PCI_INT(bus_pci, 0x5, 0x0, 0x14);
-	  PCI_INT(bus_pci, 0x5, 0x1, 0x15);
-	  PCI_INT(bus_pci, 0x5, 0x2, 0x16);
-	  PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
-	  /* PCI_SLOT 1. */
-	  PCI_INT(bus_pci, 0x6, 0x0, 0x15);
-	  PCI_INT(bus_pci, 0x6, 0x1, 0x16);
-	  PCI_INT(bus_pci, 0x6, 0x2, 0x17);
-	  PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
-	  /* PCI_SLOT 2. */
-	  PCI_INT(bus_pci, 0x7, 0x0, 0x16);
-	  PCI_INT(bus_pci, 0x7, 0x1, 0x17);
-	  PCI_INT(bus_pci, 0x7, 0x2, 0x14);
-	  PCI_INT(bus_pci, 0x7, 0x3, 0x15);
-  }
-
-  /* PCIe Lan*/
-  PCI_INT(0x0, 0x06, 0x0, 0x13);
-
-  /* FCH PCIe PortA */
-  PCI_INT(0x0, 0x15, 0x0, 0x10);
-  /* FCH PCIe PortB */
-  PCI_INT(0x0, 0x15, 0x1, 0x11);
-  /* FCH PCIe PortC */
-  PCI_INT(0x0, 0x15, 0x2, 0x12);
-  /* FCH PCIe PortD */
-  PCI_INT(0x0, 0x15, 0x3, 0x13);
-
-  /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-  IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
-  IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
-  /* There is no extension information... */
-
-  /* Compute the checksums */
-  return mptable_finalize(mc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin))
+
+	/* Internal VGA */
+	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
+	/* SMBUS */
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+	/* HD Audio */
+	PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+
+	/* USB */
+	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+	PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+
+	/* on board NIC & Slot PCIE.  */
+
+	/* PCI slots */
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	if (dev && dev->enabled) {
+		u8 bus_pci = dev->link_list->secondary;
+
+		/* PCI_SLOT 0. */
+		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+		/* PCI_SLOT 1. */
+		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+		/* PCI_SLOT 2. */
+		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+	}
+
+	/* PCIe Lan*/
+	PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+	/* FCH PCIe PortA */
+	PCI_INT(0x0, 0x15, 0x0, 0x10);
+	/* FCH PCIe PortB */
+	PCI_INT(0x0, 0x15, 0x1, 0x11);
+	/* FCH PCIe PortC */
+	PCI_INT(0x0, 0x15, 0x2, 0x12);
+	/* FCH PCIe PortD */
+	PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
 {
-  void *v;
-  v = smp_write_floating_table(addr, 0);
-  return (unsigned long)smp_write_config_table(v);
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index 7f8eba6016..c24e42cf93 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -26,81 +26,81 @@
 
 
 u8 intr_data[] = {
-  [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
-  [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
-  [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x10,0x11,0x12,0x13
+	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
+	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x10,0x11,0x12,0x13
 };
 
 static void *smp_write_config_table(void *v)
 {
-  struct mp_config_table *mc;
-  int bus_isa;
+	struct mp_config_table *mc;
+	int bus_isa;
 
 	/*
 	 * By the time this function gets called, the IOAPIC registers
 	 * have been written so they can be read to get the correct
 	 * APIC ID and Version
 	 */
-  u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
-  u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
 
-  mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-  mptable_init(mc, LOCAL_APIC_ADDR);
-  memcpy(mc->mpc_oem, "AMD     ", 8);
+	mptable_init(mc, LOCAL_APIC_ADDR);
+	memcpy(mc->mpc_oem, "AMD     ", 8);
 
-  smp_write_processors(mc);
+	smp_write_processors(mc);
 
-  mptable_write_buses(mc, NULL, &bus_isa);
+	mptable_write_buses(mc, NULL, &bus_isa);
 
-  /* I/O APICs:   APIC ID Version State   Address */
-  smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+	/* I/O APICs:   APIC ID Version State   Address */
+	smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
 
-  u8 byte;
+	u8 byte;
 
-  for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-    outb(byte | 0x80, 0xC00);
-    outb(intr_data[byte], 0xC01);
-  }
+	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+		outb(byte | 0x80, 0xC00);
+		outb(intr_data[byte], 0xC01);
+	}
 
-  /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
-  smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
 
-  mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
 
-  /* PCI interrupts are level triggered, and are
-   * associated with a specific bus/device/function tuple.
-   */
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
 #define PCI_INT(bus, dev, fn, pin) \
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
 
-  /* APU Internal Graphic Device*/
-  PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
-  PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+	/* APU Internal Graphic Device*/
+	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
 
-  //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
-  PCI_INT(0x0, 0x14, 0x0, 0x10);
-  /* Southbridge HD Audio: */
-  PCI_INT(0x0, 0x14, 0x2, 0x12);
+	//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+	/* Southbridge HD Audio: */
+	PCI_INT(0x0, 0x14, 0x2, 0x12);
 
-  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
-  PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
-  PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
-  PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
-  PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
-  PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
+	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
 
-  /* sata */
-  PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
 
-  /* on board NIC & Slot PCIE.  */
+	/* on board NIC & Slot PCIE.  */
 
-  /* PCI slots */
+	/* PCI slots */
 	device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
@@ -123,27 +123,27 @@ static void *smp_write_config_table(void *v)
 		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
 	}
 
-  /* PCIe PortA */
-  PCI_INT(0x0, 0x15, 0x0, 0x10);
-  /* PCIe PortB */
-  PCI_INT(0x0, 0x15, 0x1, 0x11);
-  /* PCIe PortC */
-  PCI_INT(0x0, 0x15, 0x2, 0x12);
-  /* PCIe PortD */
-  PCI_INT(0x0, 0x15, 0x3, 0x13);
-
-  /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-  IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-  IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-  /* There is no extension information... */
-
-  /* Compute the checksums */
-  return mptable_finalize(mc);
+	/* PCIe PortA */
+	PCI_INT(0x0, 0x15, 0x0, 0x10);
+	/* PCIe PortB */
+	PCI_INT(0x0, 0x15, 0x1, 0x11);
+	/* PCIe PortC */
+	PCI_INT(0x0, 0x15, 0x2, 0x12);
+	/* PCIe PortD */
+	PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
 {
-  void *v;
-  v = smp_write_floating_table(addr, 0);
-  return (unsigned long)smp_write_config_table(v);
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
 }