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authorFelix Held <felix-coreboot@felixheld.de>2023-12-19 16:42:49 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-12-20 21:58:41 +0000
commite4b080ee56060843e335cad789468418f586b0b1 (patch)
tree1b856261c51e7b6c01db1a8a7ae2ba6aefedd338 /src/mainboard/amd
parent17295c8288a071fa1198bf9fe2207bbc910fe601 (diff)
mb/amd/onyx_poc/devicetree: enable UART0
UART0 is routed to a USB-serial converter chip on the Onyx board, so also enable this UART in the devicetree, so that the OS will be able to use this UART. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b2577d799fd82a0aa0c9b01324930237e204aa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/onyx_poc/devicetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/amd/onyx_poc/devicetree.cb b/src/mainboard/amd/onyx_poc/devicetree.cb
index 27a22c6501..39c681d1c4 100644
--- a/src/mainboard/amd/onyx_poc/devicetree.cb
+++ b/src/mainboard/amd/onyx_poc/devicetree.cb
@@ -200,6 +200,7 @@ chip soc/amd/genoa_poc
end
end
+ device ref uart_0 on end
device ref uart_1 on end
end