diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-10-16 13:51:51 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-02 23:45:19 +0100 |
| commit | 730a043fb6cb4dd3cb5af8f8640365727b598648 (patch) | |
| tree | 59afe45caca1a8e1682939c7e44e95344104533e /src/mainboard/amd | |
| parent | d150006c4a4584bc9933c2d8ff580a54c4f0cc2a (diff) | |
cpu/amd: Add initial AMD Family 15h support
TEST: Booted ASUS KGPE-D16 with single Opteron 6380
* Unbuffered DDR3 DIMMs tested and working
* Suspend to RAM (S3) tested and working
Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11966
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/bimini_fam10/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/mahogany_fam10/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/tilapia_fam10/romstage.c | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 3649e84f91..11d54797ea 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -119,7 +119,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x33); - cpuSetAMDMSR(); + cpuSetAMDMSR(0); post_code(0x34); amd_ht_init(sysinfo); diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index e9f240c2e4..5b39bb7304 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -121,7 +121,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x33); - cpuSetAMDMSR(); + cpuSetAMDMSR(0); post_code(0x34); amd_ht_init(sysinfo); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 6bd548bf49..5131f36d9a 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -227,7 +227,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x33); - cpuSetAMDMSR(); + cpuSetAMDMSR(0); post_code(0x34); amd_ht_init(sysinfo); diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index d49ed577a9..0804b32eca 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -121,7 +121,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x33); - cpuSetAMDMSR(); + cpuSetAMDMSR(0); post_code(0x34); amd_ht_init(sysinfo); |