diff options
| author | Fred Reitberger <reitbergerfred@gmail.com> | 2023-04-06 10:01:23 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-20 12:45:48 +0000 |
| commit | 67bc6ab1e9186952b05edc55f15e354d676346f2 (patch) | |
| tree | 9e256c87147f2fc877145adee54f85c732de465e /src/mainboard/amd | |
| parent | c706880bfe1f991f0d77decd457aca038bec1202 (diff) | |
mb/amd/birman: Enable PCIe RTD3 support
Add PCIe RTD3 support so the NVMe gets placed into D3 when entering s0i3
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I5eac65125c11dd04c5dbb5996c947ad734acdae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/birman/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/amd/birman/devicetree_phoenix.cb | 16 |
2 files changed, 15 insertions, 2 deletions
diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index d27c38b504..5d297dabc2 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS select EC_ACPI select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select AMD_SOC_CONSOLE_UART if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + select DRIVERS_PCIE_RTD3_DEVICE select MAINBOARD_HAS_CHROMEOS select PCIEXP_ASPM select PCIEXP_CLK_PM diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix.cb index ff54e1f89f..2fc78aa275 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix.cb @@ -162,12 +162,24 @@ chip soc/amd/phoenix device domain 0 on device ref iommu on end device ref gpp_bridge_1_1 on end # MXM - device ref gpp_bridge_1_2 on end # NVMe SSD1 + device ref gpp_bridge_1_2 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # NVMe SSD1 device ref gpp_bridge_1_3 on end # GBE device ref gpp_bridge_2_1 on end # SD device ref gpp_bridge_2_2 on end # WWAN device ref gpp_bridge_2_3 on end # WIFI - device ref gpp_bridge_2_4 on end # NVMe SSD0 + device ref gpp_bridge_2_4 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # NVMe SSD0 device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) |