diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-02-02 22:11:52 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-03 23:46:00 +0000 |
| commit | 556d1cc17f34615e3a08ccc9a48820a304a789a8 (patch) | |
| tree | 832a9c4ea64316f665dc3966a478dc44c4838e67 /src/mainboard/amd | |
| parent | bb42f67240c7d69a8784a03565da1239908fe402 (diff) | |
soc/amd/*/i2c: factor out common I2C pad configuration
The I2C pad control registers of Picasso and Cezanne are identical and
the one of Sabrina is a superset of it, so factor out the functionality.
To avoid having devicetree settings that contain raw register bits, the
i2c_pad_control struct is introduced and used. The old Picasso code for
this had the RX level hard-coded for 3.3V I2C interfaces, so keep it
this way in this patch but add a TODO for future improvements.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/chausie/devicetree.cb | 8 | ||||
| -rw-r--r-- | src/mainboard/amd/majolica/devicetree.cb | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index 19815b3681..6067b18ebf 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -14,10 +14,10 @@ chip soc/amd/sabrina }" # I2C Pad Control RX Select Configuration - register "i2c_pad_ctrl_rx_sel[0]" = "I2C_PAD_CTRL_RX_SEL_3_3V" - register "i2c_pad_ctrl_rx_sel[1]" = "I2C_PAD_CTRL_RX_SEL_3_3V" - register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" - register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_3_3V" + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_3_3V" register "s0ix_enable" = "true" diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index 7bb0db1e33..9758e9cf2d 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -14,10 +14,10 @@ chip soc/amd/cezanne }" # I2C Pad Control RX Select Configuration - register "i2c_pad_ctrl_rx_sel[0]" = "I2C_PAD_CTRL_RX_SEL_3_3V" - register "i2c_pad_ctrl_rx_sel[1]" = "I2C_PAD_CTRL_RX_SEL_3_3V" - register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" - register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_3_3V" + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_3_3V" register "s0ix_enable" = "true" |