diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-04-05 19:57:44 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-22 13:45:43 +0000 |
| commit | 4c548919c617d7a19482c23156a7546f0e18164f (patch) | |
| tree | 9488f0c0fe0afb10491d484c28cd70347e9459ef /src/mainboard/amd | |
| parent | 4eee50642ff5ac6e7d7830afd38693943fe17b5b (diff) | |
vc/amd/fps/phoenix/platform_descriptors: drop logical-physical mapping
For Phoenix the lane numbers in the DXIO descriptor match the ones in
the schematic, so remove the corresponding text and the table from the
comment on the fsp_dxio_descriptor struct. Since there's no logical to
physical lane number remapping needed for the lanes in the Phoenix DXIO
descriptors, drop the 'logical' from the start_logical_lane and
end_logical_lane fields in the DXIO descriptor and rename those to
start_lane and end_lane.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I94664fd9d3807370b73f9fae8645d444e5faf7b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/birman/port_descriptors_phoenix.c | 36 | ||||
| -rw-r--r-- | src/mainboard/amd/mayan/port_descriptors.c | 16 |
2 files changed, 26 insertions, 26 deletions
diff --git a/src/mainboard/amd/birman/port_descriptors_phoenix.c b/src/mainboard/amd/birman/port_descriptors_phoenix.c index d254eea030..5f4b1788bb 100644 --- a/src/mainboard/amd/birman/port_descriptors_phoenix.c +++ b/src/mainboard/amd/birman/port_descriptors_phoenix.c @@ -10,8 +10,8 @@ #define phx_mxm_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ .port_present = CONFIG(ENABLE_EVAL_CARD), \ - .start_logical_lane = 0, \ - .end_logical_lane = 7, \ + .start_lane = 0, \ + .end_lane = 7, \ .device_number = 1, \ .function_number = 1, \ .link_speed_capability = GEN3, \ @@ -25,8 +25,8 @@ #define phx2_mxm_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ .port_present = CONFIG(ENABLE_EVAL_CARD), \ - .start_logical_lane = 0, \ - .end_logical_lane = 3, \ + .start_lane = 0, \ + .end_lane = 3, \ .device_number = 1, \ .function_number = 1, \ .link_speed_capability = GEN3, \ @@ -39,8 +39,8 @@ #define phx_ssd1_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ .port_present = !CONFIG(DISABLE_DT_M2), \ - .start_logical_lane = 8, \ - .end_logical_lane = 11, \ + .start_lane = 8, \ + .end_lane = 11, \ .device_number = 1, \ .function_number = 2, \ .link_speed_capability = GEN3, \ @@ -54,8 +54,8 @@ #define phx2_ssd1_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ .port_present = true, \ - .start_logical_lane = 8, \ - .end_logical_lane = 9, \ + .start_lane = 8, \ + .end_lane = 9, \ .device_number = 1, \ .function_number = 2, \ .link_speed_capability = GEN3, \ @@ -68,8 +68,8 @@ #define gbe_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ .port_present = true, \ - .start_logical_lane = 12, \ - .end_logical_lane = 12, \ + .start_lane = 12, \ + .end_lane = 12, \ .device_number = 1, \ .function_number = 3, \ .link_speed_capability = GEN3, \ @@ -82,8 +82,8 @@ #define sd_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ .port_present = true, \ - .start_logical_lane = 13, \ - .end_logical_lane = 13, \ + .start_lane = 13, \ + .end_lane = 13, \ .device_number = 2, \ .function_number = 1, \ .link_speed_capability = GEN3, \ @@ -96,8 +96,8 @@ #define wwan_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ .port_present = true, \ - .start_logical_lane = 14, \ - .end_logical_lane = CONFIG(WWAN01) ? 15 : 14, \ + .start_lane = 14, \ + .end_lane = CONFIG(WWAN01) ? 15 : 14, \ .device_number = 2, \ .function_number = 2, \ .link_speed_capability = GEN3, \ @@ -110,8 +110,8 @@ #define wlan_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ .port_present = true, \ - .start_logical_lane = 15, \ - .end_logical_lane = CONFIG(WLAN01) ? 14 : 15, \ + .start_lane = 15, \ + .end_lane = CONFIG(WLAN01) ? 14 : 15, \ .device_number = 2, \ .function_number = 3, \ .link_speed_capability = GEN3, \ @@ -124,8 +124,8 @@ #define ssd0_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ .port_present = true, \ - .start_logical_lane = 16, \ - .end_logical_lane = 19, \ + .start_lane = 16, \ + .end_lane = 19, \ .device_number = 2, \ .function_number = 4, \ .link_speed_capability = GEN3, \ diff --git a/src/mainboard/amd/mayan/port_descriptors.c b/src/mainboard/amd/mayan/port_descriptors.c index 6654806c50..c2e267c7cc 100644 --- a/src/mainboard/amd/mayan/port_descriptors.c +++ b/src/mainboard/amd/mayan/port_descriptors.c @@ -13,8 +13,8 @@ static const fsp_dxio_descriptor mayan_dxio_descriptors[] = { // MXM .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 0, - .end_logical_lane = 3, + .start_lane = 0, + .end_lane = 3, .device_number = 1, .function_number = 1, .link_speed_capability = GEN_MAX, @@ -33,8 +33,8 @@ static const fsp_dxio_descriptor mayan_dxio_descriptors[] = { // M2 SSD0-NVME .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 16, - .end_logical_lane = 19, + .start_lane = 16, + .end_lane = 19, .device_number = 2, .function_number = 4, .link_speed_capability = GEN_MAX, @@ -53,8 +53,8 @@ static const fsp_dxio_descriptor mayan_dxio_descriptors[] = { // X1 .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 12, - .end_logical_lane = 12, + .start_lane = 12, + .end_lane = 12, .device_number = 1, .function_number = 3, .link_speed_capability = GEN_MAX, @@ -72,8 +72,8 @@ static const fsp_dxio_descriptor mayan_dxio_descriptors[] = { // DT .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 8, - .end_logical_lane = 9, + .start_lane = 8, + .end_lane = 9, .device_number = 1, .function_number = 2, .link_speed_capability = GEN_MAX, |