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authorMike Banon <mikebdp2@gmail.com>2020-02-13 16:25:10 +0000
committerPatrick Georgi <pgeorgi@google.com>2020-02-24 13:56:23 +0000
commit0bed4c84cc73870bb9757fc5229d33032ff71b5b (patch)
tree028ab75f98f4cdf607ca811a56f6e8415db23c01 /src/mainboard/amd
parent0dcbcd31918cd0dd7e4f1086649dfe4a04397633 (diff)
mb/amd/thatcher: Switch away from ROMCC_BOOTBLOCK
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I948eeaaeb7975561fffc1218c70dba6a784101fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/38877 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/thatcher/Kconfig4
-rw-r--r--src/mainboard/amd/thatcher/Kconfig.name4
-rw-r--r--src/mainboard/amd/thatcher/Makefile.inc2
-rw-r--r--src/mainboard/amd/thatcher/bootblock.c (renamed from src/mainboard/amd/thatcher/romstage.c)38
4 files changed, 13 insertions, 35 deletions
diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig
index e55659225f..e1c5aee487 100644
--- a/src/mainboard/amd/thatcher/Kconfig
+++ b/src/mainboard/amd/thatcher/Kconfig
@@ -13,14 +13,10 @@
# GNU General Public License for more details.
#
-config BOARD_AMD_THATCHER
- def_bool n
-
if BOARD_AMD_THATCHER
config BOARD_SPECIFIC_OPTIONS
def_bool y
- #select ROMCC_BOOTBLOCK
select CPU_AMD_AGESA_FAMILY15_TN
select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
select SOUTHBRIDGE_AMD_AGESA_HUDSON
diff --git a/src/mainboard/amd/thatcher/Kconfig.name b/src/mainboard/amd/thatcher/Kconfig.name
index b57bdb9a7f..aff5246cc7 100644
--- a/src/mainboard/amd/thatcher/Kconfig.name
+++ b/src/mainboard/amd/thatcher/Kconfig.name
@@ -1,2 +1,2 @@
-#config BOARD_AMD_THATCHER
-# bool"Thatcher"
+config BOARD_AMD_THATCHER
+ bool "Thatcher"
diff --git a/src/mainboard/amd/thatcher/Makefile.inc b/src/mainboard/amd/thatcher/Makefile.inc
index f8895faa92..4dde2cfd1e 100644
--- a/src/mainboard/amd/thatcher/Makefile.inc
+++ b/src/mainboard/amd/thatcher/Makefile.inc
@@ -13,6 +13,8 @@
# GNU General Public License for more details.
#
+bootblock-y += bootblock.c
+
romstage-y += buildOpts.c
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/bootblock.c
index dff516ca3a..d25102541c 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/bootblock.c
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@@ -13,42 +11,24 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
#include <amdblocks/acpimmio.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <console/console.h>
+#include <bootblock_common.h>
+#include <stdint.h>
#include <device/pci_ops.h>
-#include <amdblocks/acpimmio.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
+#include <console/console.h>
#include <superio/smsc/lpc47n217/lpc47n217.h>
#define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1)
-void board_BeforeAgesa(struct sysinfo *cb)
+void bootblock_mainboard_early_init(void)
{
- u8 byte;
- pci_devfn_t dev;
-
- /* Set LPC decode enables. */
- dev = PCI_DEV(0, 0x14, 3);
-
- byte = pci_read_config8(dev, 0x48);
- byte |= 3; /* 2e, 2f */
- pci_write_config8(dev, 0x48, byte);
-
post_code(0x30);
- /* For serial port. */
- pci_write_config32(dev, 0x44, 0xff03ffd5);
- byte = pci_read_config8(dev, 0x48);
- byte |= 3; /* 2e, 2f */
- pci_write_config8(dev, 0x48, byte);
-
post_code(0x31);
- lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- pm_io_write8(0x24, 1);
- pm_io_write8(0xea, 1);
gpio_100_write8(0x1, 0x98);
+
+ /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
+ pm_write8(0xea, 0x1);
+
+ lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}