simplify source tree hierarchy: move files from sdram/ and ram/ to lib/

It's only three files. Also fix up all the paths (Gotta love included C files)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

7 files changed, 10 insertions, 10 deletions

diff --git a/src/mainboard/amd/db800/cache_as_ram_auto.c b/src/mainboard/amd/db800/cache_as_ram_auto.c
index 0ea76445aa..f0e37d7306 100644
--- a/src/mainboard/amd/db800/cache_as_ram_auto.c
+++ b/src/mainboard/amd/db800/cache_as_ram_auto.c
@@ -27,7 +27,7 @@
 #include <arch/hlt.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
+#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>
@@ -55,7 +55,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
-#include "sdram/generic_sdram.c"
+#include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
 
diff --git a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
index 75ff96c338..b058b445f3 100644
--- a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
+++ b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
@@ -88,7 +88,7 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
+#include "lib/generic_sdram.c"
 #include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/amd/norwich/cache_as_ram_auto.c b/src/mainboard/amd/norwich/cache_as_ram_auto.c
index aae92deb9b..fc7e96b342 100644
--- a/src/mainboard/amd/norwich/cache_as_ram_auto.c
+++ b/src/mainboard/amd/norwich/cache_as_ram_auto.c
@@ -27,7 +27,7 @@
 #include <arch/hlt.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
+#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>
@@ -53,7 +53,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
-#include "sdram/generic_sdram.c"
+#include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
 
diff --git a/src/mainboard/amd/pistachio/cache_as_ram_auto.c b/src/mainboard/amd/pistachio/cache_as_ram_auto.c
index bbe96ce978..4615901fe7 100644
--- a/src/mainboard/amd/pistachio/cache_as_ram_auto.c
+++ b/src/mainboard/amd/pistachio/cache_as_ram_auto.c
@@ -82,7 +82,7 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
+#include "lib/generic_sdram.c"
 #include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index e1326ff622..e8f590d566 100644
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -8,7 +8,7 @@
 #include <arch/hlt.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
+#include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
@@ -93,7 +93,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 }
 
 #include "northbridge/amd/gx2/raminit.c"
-#include "sdram/generic_sdram.c"
+#include "lib/generic_sdram.c"
 
 #define PLLMSRhi 0x00001490
 #define PLLMSRlo 0x02000030
diff --git a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
index fb1be8dd28..7d28715e37 100644
--- a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
+++ b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
@@ -126,7 +126,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "northbridge/amd/amdk8/raminit_f.c"
 
-#include "sdram/generic_sdram.c"
+#include "lib/generic_sdram.c"
 
  /* tyan does not want the default */
 #include "resourcemap.c" 
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
index 4e484553f7..abb28917c1 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
@@ -63,7 +63,7 @@ static void post_code(u8 value) {
 #if (CONFIG_USE_FAILOVER_IMAGE == 0)
 #include "arch/i386/lib/console.c"
 #include "pc80/serial.c"
-#include "ram/ramtest.c"
+#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"