mb/amd/mandolin: factor out port descriptors from mainboard.c

Change-Id: Ia2101cc0bae0d68cea1954424d18833aa22670c6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42784
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 209 insertions, 208 deletions

diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc
index 52ad9c695b..56dd5e2454 100644
--- a/src/mainboard/amd/mandolin/Makefile.inc
+++ b/src/mainboard/amd/mandolin/Makefile.inc
@@ -4,6 +4,7 @@ bootblock-y += bootblock.c
 bootblock-y += early_gpio.c
 
 ramstage-y += gpio.c
+ramstage-y += port_descriptors.c
 
 # APCB_mandolin.bin
 APCB_SOURCES = mandolin
diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c
index 54f5775772..c0b9dac7ba 100644
--- a/src/mainboard/amd/mandolin/mainboard.c
+++ b/src/mainboard/amd/mandolin/mainboard.c
@@ -8,8 +8,6 @@
 #include <soc/cpu.h>
 #include <soc/southbridge.h>
 #include <soc/pci_devs.h>
-#include <soc/platform_descriptors.h>
-#include <soc/soc_util.h>
 #include <types.h>
 #include <commonlib/helpers.h>
 #include <chip.h>
@@ -119,212 +117,6 @@ static void mainboard_init(void *chip_info)
 	mainboard_program_gpios();
 }
 
-static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
-	{ /* MXM */
-		.port_present = true,
-		.engine_type = PCIE_ENGINE,
-		.start_lane = 8,
-		.end_lane = 15,
-		.device_number = 1,
-		.function_number = 1,
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ6
-	},
-	{ /* SSD */
-		.port_present = true,
-		.engine_type = PCIE_ENGINE,
-		.start_lane = 0,
-		.end_lane = 1,
-		.device_number = 1,
-		.function_number = 7,
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ5
-	},
-	{ /* WLAN */
-		.port_present = true,
-		.engine_type = PCIE_ENGINE,
-		.start_lane = 4,
-		.end_lane = 4,
-		.device_number = 1,
-		.function_number = 2,
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ0
-	},
-	{ /* LAN */
-		.port_present = true,
-		.engine_type = PCIE_ENGINE,
-		.start_lane = 5,
-		.end_lane = 5,
-		.device_number = 1,
-		.function_number = 3,
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ1
-	},
-	{ /* WWAN */
-		.port_present = true,
-		.engine_type = PCIE_ENGINE,
-		.start_lane = 2,
-		.end_lane = 2,
-		.device_number = 1,
-		.function_number = 4,
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ2
-	},
-	{ /* WIFI */
-		.port_present = true,
-		.engine_type = PCIE_ENGINE,
-		.start_lane = 3,
-		.end_lane = 3,
-		.gpio_group_id = 1,
-		.device_number = 1,
-		.function_number = 5,
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ3
-	},
-	{ /* SATA EXPRESS */
-		.port_present = true,
-		.engine_type = SATA_ENGINE,
-		.start_lane = 6,
-		.end_lane = 7,
-		.gpio_group_id = 1,
-		.channel_type = SATA_CHANNEL_LONG,
-	}
-};
-
-static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
-	{ // MXM
-		.port_present = true,
-		.engine_type = PCIE_ENGINE,
-		.start_lane = 8,
-		.end_lane = 11,
-		.device_number = 1,
-		.function_number = 1,
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ6
-	},
-	{ // SSD
-		.port_present = true,
-		.engine_type = PCIE_ENGINE,
-		.start_lane = 0,
-		.end_lane = 1,
-		.device_number = 1,
-		.function_number = 7,
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ5
-	},
-	{ // WLAN
-		.port_present = true,
-		.engine_type = PCIE_ENGINE,
-		.start_lane = 4,
-		.end_lane = 4,
-		.device_number = 1,
-		.function_number = 2,
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ0
-	},
-	{ // LAN
-		.port_present = true,
-		.engine_type = PCIE_ENGINE,
-		.start_lane = 5,
-		.end_lane = 5,
-		.device_number = 1,
-		.function_number = 3,
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ1
-	}
-};
-
-static const fsp_ddi_descriptor pco_ddi_descriptors[] = {
-	{ // DDI0 - DP
-		.connector_type = DP,
-		.aux_index = AUX1,
-		.hdp_index = HDP1
-	},
-	{ /* DDI1 - eDP */
-		.connector_type = EDP,
-		.aux_index = AUX2,
-		.hdp_index = HDP2
-	},
-	{ /* DDI2 - DP */
-		.connector_type = DP,
-		.aux_index = AUX3,
-		.hdp_index = HDP3,
-	},
-	{ /* DDI3 - DP */
-		.connector_type = DP,
-		.aux_index = AUX4,
-		.hdp_index = HDP4,
-	}
-};
-
-static const fsp_ddi_descriptor dali_ddi_descriptors[] = {
-	{ // DDI0 - DP
-		.connector_type = DP,
-		.aux_index = AUX1,
-		.hdp_index = HDP1
-	},
-	{ // DDI1 - eDP
-		.connector_type = EDP,
-		.aux_index = AUX2,
-		.hdp_index = HDP2
-	},
-	{ // DDI2 - DP
-		.connector_type = DP,
-		.aux_index = AUX3,
-		.hdp_index = HDP3,
-	}
-};
-
-void mainboard_get_pcie_ddi_descriptors(
-		const fsp_pcie_descriptor **pcie_descs, size_t *pcie_num,
-		const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
-{
-	/* Dali */
-	if (soc_is_reduced_io_sku()) {
-		*pcie_descs = dali_pcie_descriptors;
-		*pcie_num = ARRAY_SIZE(dali_pcie_descriptors);
-		*ddi_descs = dali_ddi_descriptors;
-		*ddi_num = ARRAY_SIZE(dali_ddi_descriptors);
-	}
-	/* Picasso and default */
-	else {
-		*pcie_descs = pco_pcie_descriptors;
-		*pcie_num = ARRAY_SIZE(pco_pcie_descriptors);
-		*ddi_descs = pco_ddi_descriptors;
-		*ddi_num = ARRAY_SIZE(pco_ddi_descriptors);
-	}
-}
-
 static void mandolin_enable(struct device *dev)
 {
 	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
diff --git a/src/mainboard/amd/mandolin/port_descriptors.c b/src/mainboard/amd/mandolin/port_descriptors.c
new file mode 100644
index 0000000000..d8969b2a66
--- /dev/null
+++ b/src/mainboard/amd/mandolin/port_descriptors.c
@@ -0,0 +1,208 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/platform_descriptors.h>
+#include <soc/soc_util.h>
+#include <types.h>
+
+static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
+	{ /* MXM */
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_lane = 8,
+		.end_lane = 15,
+		.device_number = 1,
+		.function_number = 1,
+		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ6
+	},
+	{ /* SSD */
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_lane = 0,
+		.end_lane = 1,
+		.device_number = 1,
+		.function_number = 7,
+		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ5
+	},
+	{ /* WLAN */
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_lane = 4,
+		.end_lane = 4,
+		.device_number = 1,
+		.function_number = 2,
+		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ0
+	},
+	{ /* LAN */
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_lane = 5,
+		.end_lane = 5,
+		.device_number = 1,
+		.function_number = 3,
+		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ1
+	},
+	{ /* WWAN */
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_lane = 2,
+		.end_lane = 2,
+		.device_number = 1,
+		.function_number = 4,
+		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ2
+	},
+	{ /* WIFI */
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_lane = 3,
+		.end_lane = 3,
+		.gpio_group_id = 1,
+		.device_number = 1,
+		.function_number = 5,
+		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ3
+	},
+	{ /* SATA EXPRESS */
+		.port_present = true,
+		.engine_type = SATA_ENGINE,
+		.start_lane = 6,
+		.end_lane = 7,
+		.gpio_group_id = 1,
+		.channel_type = SATA_CHANNEL_LONG,
+	}
+};
+
+static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
+	{ /* MXM */
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_lane = 8,
+		.end_lane = 11,
+		.device_number = 1,
+		.function_number = 1,
+		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ6
+	},
+	{ /* SSD */
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_lane = 0,
+		.end_lane = 1,
+		.device_number = 1,
+		.function_number = 7,
+		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ5
+	},
+	{ /* WLAN */
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_lane = 4,
+		.end_lane = 4,
+		.device_number = 1,
+		.function_number = 2,
+		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ0
+	},
+	{ /* LAN */
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_lane = 5,
+		.end_lane = 5,
+		.device_number = 1,
+		.function_number = 3,
+		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ1
+	}
+};
+
+static const fsp_ddi_descriptor pco_ddi_descriptors[] = {
+	{ /* DDI0 - DP */
+		.connector_type = DP,
+		.aux_index = AUX1,
+		.hdp_index = HDP1
+	},
+	{ /* DDI1 - eDP */
+		.connector_type = EDP,
+		.aux_index = AUX2,
+		.hdp_index = HDP2
+	},
+	{ /* DDI2 - DP */
+		.connector_type = DP,
+		.aux_index = AUX3,
+		.hdp_index = HDP3,
+	},
+	{ /* DDI3 - DP */
+		.connector_type = DP,
+		.aux_index = AUX4,
+		.hdp_index = HDP4,
+	}
+};
+
+static const fsp_ddi_descriptor dali_ddi_descriptors[] = {
+	{ /* DDI0 - DP */
+		.connector_type = DP,
+		.aux_index = AUX1,
+		.hdp_index = HDP1
+	},
+	{ /* DDI1 - eDP */
+		.connector_type = EDP,
+		.aux_index = AUX2,
+		.hdp_index = HDP2
+	},
+	{ /* DDI2 - DP */
+		.connector_type = DP,
+		.aux_index = AUX3,
+		.hdp_index = HDP3,
+	}
+};
+
+void mainboard_get_pcie_ddi_descriptors(
+		const fsp_pcie_descriptor **pcie_descs, size_t *pcie_num,
+		const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
+{
+	if (soc_is_reduced_io_sku()) { /* Dali */
+		*pcie_descs = dali_pcie_descriptors;
+		*pcie_num = ARRAY_SIZE(dali_pcie_descriptors);
+		*ddi_descs = dali_ddi_descriptors;
+		*ddi_num = ARRAY_SIZE(dali_ddi_descriptors);
+	} else { /* Picasso and default */
+		*pcie_descs = pco_pcie_descriptors;
+		*pcie_num = ARRAY_SIZE(pco_pcie_descriptors);
+		*ddi_descs = pco_ddi_descriptors;
+		*ddi_num = ARRAY_SIZE(pco_ddi_descriptors);
+	}
+}