amdk8/amdfam10: Use CAR_GLOBAL for sysinfo

This gets rid of the somewhat unstructured placement of AMD's
sysinfo structure in CAR.
We used to carve out some CAR space using a Kconfig variable,
and then put sysinfo there manually (by "virtue" of pointer magic).

Now it's a variable with the CAR_GLOBAL qualifier, and build
system magic.

For this, the following steps were done (but must happen together
since the intermediates won't build):
- Add new CAR_GLOBAL sysinfo_car
- point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR
- remove DCACHE_RAM_GLOBAL_VAR_SIZE
  - from CAR setup (no need to reserve the space)
  - commented out code (that was commented out for years)
  - only copy sizeof(sysinfo) into RAM after ram init, where
    before it copied the whole GLOBAL_VAR area.
  - from Kconfig

Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1887
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>

12 files changed, 10 insertions, 27 deletions

diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 5980ca2a2e..b62b91f4ae 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -79,7 +79,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 84b08e6179..35d59648e6 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -72,7 +72,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 bsp_apicid = 0;
 	msr_t msr;
 	struct cpuid_result cpuid1;
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */
diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig
index 96514b1856..2a6f4eacd5 100644
--- a/src/mainboard/amd/mahogany/Kconfig
+++ b/src/mainboard/amd/mahogany/Kconfig
@@ -34,10 +34,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x0
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 39070eaae7..50821f994a 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -73,7 +73,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 bsp_apicid = 0;
 	msr_t msr;
 	struct cpuid_result cpuid1;
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index d48b69d24a..9dd35bd9d4 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -76,7 +76,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;
diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig
index edf931ac54..febf265113 100644
--- a/src/mainboard/amd/pistachio/Kconfig
+++ b/src/mainboard/amd/pistachio/Kconfig
@@ -31,10 +31,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x0
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index fe37842093..7385b658d3 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -67,9 +67,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 bsp_apicid = 0;
 	msr_t msr;
 	struct cpuid_result cpuid1;
-	struct sys_info *sysinfo =
-	    (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
-				CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */
diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig
index 1e5e625e93..26fa45f2be 100644
--- a/src/mainboard/amd/serengeti_cheetah/Kconfig
+++ b/src/mainboard/amd/serengeti_cheetah/Kconfig
@@ -38,10 +38,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x8
diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
index 84561d6b1a..710eae8d03 100644
--- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
@@ -41,11 +41,8 @@ static inline unsigned get_nodes(void)
 
 void hardwaremain(int ret_addr)
 {
-	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE +
-			CONFIG_DCACHE_RAM_SIZE -
-			CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-	struct sys_info *sysinfox = ((CONFIG_RAMTOP) -
-			CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfo = &sysinfo_car; // in CACHE
+	struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM
 
 	struct node_core_id id;
 
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index a70baaaa2c..db8cdb0bae 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -110,7 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	};
 
-	struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
         int needs_reset;
         unsigned bsp_apicid = 0;
 #if CONFIG_SET_FIDVID
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 09447a63c1..b016e5d56a 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -190,7 +190,7 @@ static const u8 spd_addr[] = {
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	u32 bsp_apicid = 0, val;
 	msr_t msr;
 
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 9919cce880..6e0ad25f10 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -76,7 +76,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;