diff options
| author | Kerry She <shekairui@gmail.com> | 2011-08-18 18:03:44 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-09-07 01:08:57 +0200 |
| commit | feed329a0c006968242aa3065506b5f37f4308d4 (patch) | |
| tree | 0ef0e9e0c112230dd03fe14e199b0be74776b112 /src/mainboard/amd/torpedo/BiosCallOuts.c | |
| parent | 16d3ec6a58b7a7ba52d4d17299b977e5c3e0557f (diff) | |
AMD F14 southbridge update
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.
Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/torpedo/BiosCallOuts.c')
| -rwxr-xr-x | src/mainboard/amd/torpedo/BiosCallOuts.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index ff55e2470a..bd6c633c65 100755 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -525,7 +525,6 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) UINT32 GpioMmioAddr; UINT8 Data8; UINT16 Data16; - UINT8 TempData8; FcnData = Data; MemData = ConfigPtr; @@ -598,14 +597,14 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; if (ResetInfo->ResetControl == DeassertSlotReset) { - if (ResetInfo->ResetId & BIT2+BIT3) { //de-assert + if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45); if (Data8 & BIT7) { Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); while (!(Data8 & BIT7)) { Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); - } + } // GPIO44: PE_GPIO0 MXM Reset Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); Data8 |= BIT6 ; |