diff options
| author | Bruce Griffith <Bruce.Griffith@se-eng.com> | 2013-04-23 14:31:55 -0600 |
|---|---|---|
| committer | Martin Roth <martin.roth@se-eng.com> | 2013-05-01 23:49:06 +0200 |
| commit | 5c2025c40f747c383e6106799f06c4a92cd07201 (patch) | |
| tree | 5c55b07adf009352f8a1bca77bd6d9c9f32a4ec8 /src/mainboard/amd/thatcher | |
| parent | 052942923b2320ee9cb2a1bcc2d2689c179ad4f5 (diff) | |
AMD Hudson A55E: Remove GEC firmware blob kconfig prompt
The "gigabit ethernet controller" (GEC) block was added to AMD
Hudson A55E to integrate ethernet capabilities into an AMD
southbridge.
The GEC is designed to work with B50610 and B50610M gigabit PHY
chips from Broadcom. These parts may not be generally available
in small quantities for embedded development.
The GEC block requires an opaque firmware blob to function. The
GEC blob is controlled by AMD and Broadcom and is not available
from coreboot.org.
This change removes GEC support from AMD Parmer and AMD Thatcher
mainboards since these boards do not have the Broadcom PHY.
AMD has requested that the GEC be hidden for Hudson FCH since
the PHY parts are not generally available. This Kconfig option
can make it appear that this is a viable and supported way to
add Ethernet to an embedded board. It is possible to use the
Hudson GEC block with other PHYs, but this requires development
of a custom GEC blob and a custom Ethernet driver. A custom GEC
blob has been developed for a Micrel PHY, but there is no
accompanying driver.
Change-Id: I7a7bf4d41e453390ecf987c9c45ef2434fc1f1a3
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3127
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Diffstat (limited to 'src/mainboard/amd/thatcher')
| -rw-r--r-- | src/mainboard/amd/thatcher/BiosCallOuts.c | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/thatcher/agesawrapper.c | 1 |
2 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index e0af994493..9a3f61c0c0 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -269,7 +269,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) * Fch Oem setting callback * * Configure platform specific Hudson device, - * such Azalia, SATA, GEC, IMC etc. + * such Azalia, SATA, IMC etc. */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index df45148c2c..f7577fdc3d 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -559,7 +559,6 @@ STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; - FchParams->Gec.GecShadowRomBase = UserOptions.FchBldCfg->CfgGecShadowRomBase; FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; |