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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-03-04 07:50:54 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-24 10:31:50 +0000 |
commit | acc8ac649d1cf8a35e3407b8ca055aef9e9371b0 (patch) | |
tree | 7d9b6ec12e05c8d786fae2047255020f5bb1eb5e /src/mainboard/amd/thatcher/romstage.c | |
parent | 46379c74ad829863a616e0d35aeea9c7fd344c33 (diff) |
amd/thatcher: Switch away from AGESA_LEGACY
Change-Id: I7194eb910cccc454c5f20c23629ff2a45b1a9079
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd/thatcher/romstage.c')
-rw-r--r-- | src/mainboard/amd/thatcher/romstage.c | 82 |
1 files changed, 17 insertions, 65 deletions
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index b080c3f065..4f7a872ba5 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -22,89 +22,41 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesa_helper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> + #include <superio/smsc/lpc47n217/lpc47n217.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; u8 byte; pci_devfn_t dev; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - /* Set LPC decode enables. */ dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); + byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ pci_write_config8(dev, 0x48, byte); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - outb(0xea, 0xcd6); - outb(0x1, 0xcd7); - *(u8 *)0xfed80101 = 0x98; - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } + post_code(0x30); + /* For serial port. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); - post_code(0x50); - copy_and_run(); + post_code(0x31); + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - post_code(0x54); /* Should never see this post code. */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + outb(0xea, 0xcd6); + outb(0x1, 0xcd7); + *(u8 *)0xfed80101 = 0x98; } |