AGESA fam14 boards: Clean up devicetree

Remove double nesting of chip northbridge/amd.
There is requirement to keep SPD address map in
the same chip block with device 0:18.2.

Change-Id: Ib212f24c3d697a009d2ca8e2c77220de4bfb7573
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30733
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 75 insertions, 81 deletions

diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb
index 0488f5ba92..ccb60ffae0 100644
--- a/src/mainboard/amd/south_station/devicetree.cb
+++ b/src/mainboard/amd/south_station/devicetree.cb
@@ -15,93 +15,87 @@
 chip northbridge/amd/agesa/family14/root_complex
         device cpu_cluster 0 on
                 chip cpu/amd/agesa/family14
-                  device lapic 0 on end
+			device lapic 0 on end
                 end
         end
         device domain 0 on
                 subsystemid 0x1022 0x1510 inherit
-                chip northbridge/amd/agesa/family14 # CPU side of HT root complex
-#                       device pci 18.0 on #  northbridge
-                                chip northbridge/amd/agesa/family14 # PCI side of HT root complex
-                                        device pci 0.0 on end # Root Complex
-                                        device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
-                                        device pci 1.1 on end # Internal HDMI Audio
-                                        device pci 4.0 on end # PCIE P2P bridge 0x9604
-                                        device pci 5.0 on end # PCIE P2P bridge 0x9605
-                                        device pci 6.0 on end # PCIE P2P bridge 0x9606
-                                        device pci 7.0 on end # PCIE P2P bridge 0x9607
-                                        device pci 8.0 on end # NB/SB Link P2P bridge
-                                end # agesa northbridge
+		chip northbridge/amd/agesa/family14
+			device pci 0.0 on end # Root Complex
+			device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
+			device pci 1.1 on end # Internal HDMI Audio
+			device pci 4.0 on end # PCIE P2P bridge 0x9604
+			device pci 5.0 on end # PCIE P2P bridge 0x9605
+			device pci 6.0 on end # PCIE P2P bridge 0x9606
+			device pci 7.0 on end # PCIE P2P bridge 0x9607
+			device pci 8.0 on end # NB/SB Link P2P bridge
+		end # agesa northbridge
 
-                                chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
-                                        device pci 11.0 on end # SATA
-                                        device pci 12.0 on end # USB
-                                        device pci 12.1 on end # USB
-                                        device pci 12.2 on end # USB
-                                        device pci 13.0 on end # USB
-                                        device pci 13.1 on end # USB
-                                        device pci 13.2 on end # USB
-                                        device pci 14.0 on # SM
-##                                                chip drivers/generic/generic #dimm 0-0-0
-##                                                        device i2c 50 on end
-##                                                end
-##                                                chip drivers/generic/generic #dimm 0-0-1
-##                                                        device i2c 51 on end
-##                                                end
-                                        end # SM
-                                        device pci 14.1 on end # IDE    0x439c
-                                        device pci 14.2 on end # HDA    0x4383
-                                        device pci 14.3 on # LPC        0x439d
-					        chip superio/fintek/f81865f
-							device pnp 4e.0 off		# Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 4e.3 off end			# Parallel Port
-							device pnp 4e.4 off end			# Hardware Monitor
-							device pnp 4e.5 on #  Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-							end
-							device pnp 4e.6 off end			# GPIO
-							device pnp 4e.a off end			# PME
-							device pnp 4e.10 on			# COM1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 4e.11 off			# COM2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-                                                end # f81865f
-					end #LPC
-					device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-	  				device pci 14.5 on  end # USB 2
-					device pci 15.0 off end # PCIe PortA
-					device pci 15.1 off end # PCIe PortB
-					device pci 15.2 off end # PCIe PortC
-					device pci 15.3 off end # PCIe PortD
-					device pci 16.0 off end # OHCI USB3
-					device pci 16.2 off end # EHCI USB3
-					register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
-		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-				end	#southbridge/amd/cimx/sb800
-#                       end #  device pci 18.0
-# These seem unnecessary
-                        device pci 18.1 on end
-                        device pci 18.2 on end
-                        device pci 18.3 on end
-                        device pci 18.4 on end
-                        device pci 18.5 on end
+		chip southbridge/amd/cimx/sb800
+			device pci 11.0 on end # SATA
+			device pci 12.0 on end # USB
+			device pci 12.1 on end # USB
+			device pci 12.2 on end # USB
+			device pci 13.0 on end # USB
+			device pci 13.1 on end # USB
+			device pci 13.2 on end # USB
+			device pci 14.0 on end # SM
+			device pci 14.1 on end # IDE    0x439c
+			device pci 14.2 on end # HDA    0x4383
+			device pci 14.3 on # LPC        0x439d
+				chip superio/fintek/f81865f
+					device pnp 4e.0 off		# Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 4e.3 off end			# Parallel Port
+					device pnp 4e.4 off end			# Hardware Monitor
+					device pnp 4e.5 on #  Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+					end
+					device pnp 4e.6 off end			# GPIO
+					device pnp 4e.a off end			# PME
+					device pnp 4e.10 on			# COM1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 4e.11 off			# COM2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+				end # f81865f
+			end #LPC
+			device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
+			device pci 14.5 on  end # USB 2
+			device pci 15.0 off end # PCIe PortA
+			device pci 15.1 off end # PCIe PortB
+			device pci 15.2 off end # PCIe PortC
+			device pci 15.3 off end # PCIe PortD
+			device pci 16.0 off end # OHCI USB3
+			device pci 16.2 off end # EHCI USB3
+			register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
+			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+		end	#southbridge/amd/cimx/sb800
 
-                        register "spdAddrLookup" = "
-                        {
-                            { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-                            { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-                        }"
+		chip northbridge/amd/agesa/family14
+
+			# These seem unnecessary
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+			device pci 18.5 on end
+
+			register "spdAddrLookup" = "
+			{
+			    { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+			    { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+			}"
+
+		end # agesa northbridge
 
-                end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
         end #domain
 end #northbridge/amd/agesa/family14/root_complex