aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/amd/south_station/romstage.c
diff options
context:
space:
mode:
authorKerry Sheh <shekairui@gmail.com>2011-11-15 21:27:07 +0800
committerMarc Jones <marcj303@gmail.com>2011-11-18 21:38:59 +0100
commitb79935129a561eb33cdba06a3a0f65d2e350924c (patch)
tree1a70164c42ea4fcc07871734fbfe6a5d1b1254c4 /src/mainboard/amd/south_station/romstage.c
parent6f7b1589fa82a2cc654e4f35ce2dc0787d84ce0f (diff)
mainboard: Add AMD southstation RDK support
AMD southstation Reference Design Kit is designed for NAS application. This platform using family14 RevC0 processor, SB850 southbridge. Vgabios and Promise RAID Option ROM is required for hardware RAID support, can retrieve from the AMD NDA website. Verified feature: HDMI, LAN, usb and mini-pcie slot. RAID0, RAID1 RAID10 and RAID5 upto 6 sata hard drive with ubuntu server 10.10. Change-Id: I16e6f5dab8b0d634e186068c81436db77fb4475a Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/433 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/amd/south_station/romstage.c')
-rw-r--r--src/mainboard/amd/south_station/romstage.c110
1 files changed, 110 insertions, 0 deletions
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
new file mode 100644
index 0000000000..95f27bd0ae
--- /dev/null
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <lib.h>
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <console/loglevel.h>
+#include "agesawrapper.h"
+#include "cpu/x86/bist.h"
+#include "superio/fintek/f81865f/f81865f_early_serial.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "sb_cimx.h"
+#include "SBPLATFORM.h"
+
+#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+
+ // all cores: allow caching of flash chip code and data
+ // (there are no cache-as-ram reliability concerns with family 14h)
+ __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
+ __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+
+ // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+ __writemsr (0xc0010062, 0);
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+ sb_Poweron_Init();
+
+ post_code(0x31);
+ f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ // Load MPB
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+ post_code(0x35);
+ val = agesawrapper_amdinitmmio();
+
+ post_code(0x37);
+ val = agesawrapper_amdinitreset();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+ }
+
+ post_code(0x38);
+ printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
+
+ post_code(0x39);
+ val = agesawrapper_amdinitearly ();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+
+ post_code(0x40);
+ val = agesawrapper_amdinitpost ();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+
+ post_code(0x41);
+ val = agesawrapper_amdinitenv ();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+
+ post_code(0x50);
+ copy_and_run(0);
+
+ post_code(0x54); // Should never see this post code.
+}
+