diff options
| author | Patrick Georgi <patrick@georgi-clan.de> | 2012-02-16 20:44:20 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-02-17 19:04:31 +0100 |
| commit | 472efa604158c193bdcd8f357ca52c41eca53ca5 (patch) | |
| tree | b44dbe7045988d316f03a807ef34fc360e2ca31a /src/mainboard/amd/south_station/PlatformGnbPcieComplex.h | |
| parent | d13e4167a903c1bd69c9ed708987f016dff13d1d (diff) | |
Remove whitespace.
Fix issues reported by new lint test.
Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/south_station/PlatformGnbPcieComplex.h')
| -rw-r--r-- | src/mainboard/amd/south_station/PlatformGnbPcieComplex.h | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h index f35d8db723..b51089f7f6 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h @@ -25,42 +25,42 @@ #include "amdlib.h" //GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced @@ -68,5 +68,5 @@ VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ); - + #endif //_PLATFORM_GNB_PCIE_COMPLEX_H |