- Minor mod to reset16.inc to work with newer binutils hopefully this works with older ones...

- Update apic.h to include the APIC_TASK_PRI register definition
- Update mptable.c to have a reasonable board OEM and productid
- Additional testfiles for romcc.
- Split out auto.c and early failover.c moving their generic bits elsewere
- Enable cache of the rom
- Fixes to amd8111_lpc.c so that we successfully setup virtual wire mode on the ioapic


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 13 insertions, 16 deletions

diff --git a/src/mainboard/amd/solo/auto.c b/src/mainboard/amd/solo/auto.c
index 33dea8e80d..e8e3976ef2 100644
--- a/src/mainboard/amd/solo/auto.c
+++ b/src/mainboard/amd/solo/auto.c
@@ -20,7 +20,9 @@ static int boot_cpu(void)
 	msr = rdmsr(0x1b);
 	bsp = !!(msr.lo & (1 << 8));
 	if (bsp) {
-		print_debug("Bootstrap cpu\r\n");
+		print_debug("Bootstrap processor\r\n");
+	} else {
+		print_debug("Application processor\r\n");
 	}
 
 	return bsp;
@@ -110,14 +112,19 @@ static void dump_spd_registers(void)
 	}
 }
 
-
-
-
 static void main(void)
 {
 	uart_init();
 	console_init();
+#if 0
+	print_debug(" XIP_ROM_BASE: ");
+	print_debug_hex32(XIP_ROM_BASE);
+	print_debug(" XIP_ROM_SIZE: ");
+	print_debug_hex32(XIP_ROM_SIZE);
+	print_debug("\r\n");
+#endif
 	if (boot_cpu() && !cpu_init_detected()) {
+		setup_default_resource_map();
 		setup_coherent_ht_domain();
 		enumerate_ht_chain();
 		print_pci_devices();
@@ -125,17 +132,7 @@ static void main(void)
 		sdram_initialize();
 
 		dump_spd_registers();
-#if 0
-		ram_fill(  0x00100000, 0x00180000);
-		ram_verify(0x00100000, 0x00180000);
-#endif
-#ifdef MEMORY_1024MB
-		ram_fill(  0x00000000, 0x00001000);
-		ram_verify(0x00000000, 0x00001000);
-#endif
-#ifdef MEMROY_512MB
-		ram_fill(  0x00000000, 0x01ffffff);
-		ram_verify(0x00000000, 0x01ffffff);
-#endif
+		/* Check the first 8M */
+		ram_check(0x00100000, 0x00800000);
 	}
 }